Search Results for "netlist"
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Showing 39 open source projects for "netlist"
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Netlist
A netlister for GEDA/Gschem
Primarilly aimed at NGSPICE, but more formats will follow. The idea behind this is that a powerful netlister is really needed if an easy to use design environment based on NGSPICE can be created. There are lots of hooks for scripting, so many different netlists maybe created from a common circuit (for worst case analysis of parametric analysis for instance) -
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a... -
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VeroRoute
Qt based Veroboard, Perfboard, and PCB layout and routing application
Cross-platform software for producing Veroboard (stripboard), Perfboard, and 1-layer or 2-layer PCB layouts. Automatically prevents short-circuits and checks for open-circuits. Pre-compiled versions available for MS Windows and 64-bit Linux Mint 20.3 (should also run on other 64-bit Linux systems that are based on Debian and support Qt version >= 5.12.8). Android APK available (tested on Android 7 and Android 10) and requires device resolution of at least 1280x800. -
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linNet
The Software for symbolic Analysis of linear Electronic Circuits
...A linear electronic circuit is a combination of the supported basic devices; these are resistor, conductance, capacitor, inductivity, operational amplifier, voltage source (constant or controlled by another voltage or current), current source (constant or controlled by voltage or another current) or a current probe (i.e. a wire). The circuit is described by a netlist. The computed formulas can be used for further investigation of the circuit or for publications or didactic purpose. An interface to GNU Octave opens up a bunch of simple to use numeric analyses and plots. -
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...However, it also offers extra functionality via applications and utilities developed by others. Electronic Design Automation (EDA) tool suites are used to provide schematic capture and editing, and schematic to netlist conversion. Waveform data viewers are used to display simulation results and PDF viewers to display user manuals.
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XSCHEM
Schematic circuit editor for VLSI and Mixed mode circuit simulation.
Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this gives top speed performance, even on very big circuits. I have succesfully managed to simulate complete VLSI projects with this tool, both digital (Verilog / VHDL) and analog (Spice). ... -
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1. flattenverilog : Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist. 2. preprocessverilog : Verilog Preprocessor to resolve macros like nested `ifdef , `define 3. createhierarchy : Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents in the higher leve 5. removehierarchy : Verilog Hierarchy Removal Tool to ungroup all the instances in a given module 6. comparemoduleinterfaces - Diff module ports and parameter. ...
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OptimWin Batch
Batch to Speedup Windows (XP-11) settings and utilities collection
https://sourceforge.net/p/optimwin-batch/ OptimWin by isidrococo at gmail This has a collection of utilities and mainly a big batch to automatically optimize and disable a huge amount of settings (Scheduled Tasks, LOGs, Services, delete Temp/Caches, etc) for Windows XP or later. Also includes a bunch of utilities, all decompressed at C:\UT Install: Decompress to a folder: 7.exe, 7z.dll, OptimWinInst.BAT, UT1.ZIP and [UT2.7z] Execute OptimWinInst.bat (some browsers deletes ".bat"... -
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ePnR
ePnR is an IC block standard cell placement & routing tool
...Standard cells are described in a simple text based library (compliant with eLogSim). Placement follows initially the cell call order in the SPICE like circuit input netlist. However, a placement optimization, aiming at minimum weighted accumulated wire length, by simulated annealing is available. Routing consists of channel routing as first step. If un-routed connections are left, Maze routing can (optionally) be applied. ePnR does not guarantee completely finished routing. However, un-routed connections will be left with rubberband connections and marked start and end points for subsequent manual routing using a third party layout editor. ePnR outputs in CIF 2.0 and GDS stream format readable by e.g. the free KLayout editor. -
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Symbolic Spice with Maxima
Maxima Script to Calculate Transfer Function of a LTspice Circuit
Script for Maxima that analyzes analog filter circuits. Reads a netlist (e.g. LTspice) and calculates the symbolic transfer function. Supported components: R, L, C, voltage, current, opamp -
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TinyCAD is a program for drawing electrical circuit diagrams commonly known as schematic drawings. It supports standard and custom symbol libraries. It supports PCB layout programs with several netlist formats and can also produce SPICE simulation netlists. It is also often used to draw one-line diagrams, block diagrams, and presentation drawings. The source code for TinyCAD is now on GitHub: https://github.com/matt123p/TinyCAD Online documentation can be found here: https://github.com/matt123p/TinyCAD/wiki
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FidoCadJ
Simple and intuitive 2D vector drawing for electronics and not only.
A multiplatform vector drawing program with a complete library of electronic symbols. Schematics and drawings are stored in a very compact text format. There is no netlist concept behind the drawings (so no simulation, and this is a choice) but this allows a great graphical flexibility and ease of use, making FidoCadJ the perfect tool for exchange sketches in forum and newsgroup discussions with a few clicks. Drawings can be exported in several graphic formats, such as pdf. Follow the development live on Twitter: https://twitter.com/davbucci -
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NetlistViewer
SPICE netlist visualizer
Please go to https://github.com/f18m/netlist-viewer for most updated code -
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Testability Measurement Tool
Performs SCOAP and PODEM algorighms on ISCAS89 Netlists.
This application calculates combinational and sequential SCOAP parameters (CC0, CC1, CO, SC0, SC1, SO) and Testability Index parameter from a ISCAS89 netlist. It also performs the PODEM algorithm to check testability of a net against a single stuck at 0 or 1 fault. -
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An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic circuits have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. ... -
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...It is an aid to Electronics Engineer who calculates transfer functions using symbolic algebra. It compute the frequency domain transfer function of a circuit in symbolic format, given a circuit description netlist in linear model. Calculate AC or DC symbolic transfer function in S-domain for Linear Circuits or Z-domain for Switching Circuits. Accept resistors, capacitors, inductors, dependent sources, ideal opamps, and ideal switches. Component values can be real numbers, symbols, or user defined symbolic expressions. Frequency domain results can be transformed to time domain via Inverse Laplace or Z Transform. ...
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spdc
simulation program for distributed circuit
This is a simulator for 3D distributed circuit based on GNU Octave. It reads a netlist describing distributed circuit parameters, stimuli, analysis types (op, ac, tran), and output controls (plot, plot3). It can also export distributed circuit to Ngspice netlist and import the corresponding Ngspice simulation result. -
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HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL
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Gnetman is primarily a netlist translator, capable of translating between formats such as VHDL, Verilog, and SPICE. Only structural gate-level netlists are supported. Various netlist manipulations are supported.
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Bliss synthesizes logic circuits in BLIF format to an equivalent SPICE netlist. Bliss is intended for use in mixed signal IC design and VLSI research.
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This set will able to generate eeschema libraries, parse KiCAD files (eeschema, eeschema library, netlist), generate Russian GOST specifications for schemes and do other actions.
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XML based parsers and translation tools for electronic design automation (EDA). Tools for manipulating netlist formats (e.g. SPICE, Spectre, CDL), languages (e.g. Verilog-AMS, VHDL-AMS, ASM), and other useful text-based formats (e.g. Liberty, Gerber).
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A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
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Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported. Project branch continues to evolve: https://github.com/gburdell/nldb including addition of tclsh UI.
