Showing 10 open source projects for "verilog netlist"

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  • 1
    GHDL

    GHDL

    VHDL 2008/93/87 simulator

    This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a...
    Downloads: 20 This Week
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  • 2
    1. flattenverilog : Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist. 2. preprocessverilog : Verilog Preprocessor to resolve macros like nested `ifdef , `define 3. createhierarchy : Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents...
    Downloads: 0 This Week
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  • 3
    XSCHEM

    XSCHEM

    Schematic circuit editor for VLSI and Mixed mode circuit simulation.

    Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this gives...
    Downloads: 18 This Week
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  • 4
    HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL
    Downloads: 0 This Week
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  • 5
    Gnetman is primarily a netlist translator, capable of translating between formats such as VHDL, Verilog, and SPICE. Only structural gate-level netlists are supported. Various netlist manipulations are supported.
    Downloads: 0 This Week
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  • 6
    Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported. Project branch continues to evolve: https://github.com/gburdell/nldb including addition of tclsh UI.
    Downloads: 0 This Week
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  • 7
    A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
    Downloads: 0 This Week
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  • 8
    XML based parsers and translation tools for electronic design automation (EDA). Tools for manipulating netlist formats (e.g. SPICE, Spectre, CDL), languages (e.g. Verilog-AMS, VHDL-AMS, ASM), and other useful text-based formats (e.g. Liberty, Gerber).
    Downloads: 0 This Week
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  • 9
    The purpose of this tool is creation of tcl/tk - based environment for convenient Verilog netlist viewing and editing. This tool will allow development of TCL scripts in order to make structural changes in verilog netlist.
    Downloads: 3 This Week
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  • 10
    This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.
    Downloads: 0 This Week
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