Search Results for "java to vhdl convertor"
Sort By:
Showing 36 open source projects for "java to vhdl convertor"
View related business solutions-
Build Securely on AWS with Proven FrameworksMoving to the cloud brings new challenges. How can you manage a larger attack surface while ensuring great network performance? Turn to Fortinet’s Tested Reference Architectures, blueprints for designing and securing cloud environments built by cybersecurity experts. Learn more and explore use cases in this white paper.
-
Test your software product anywhere in the worldGlobal App Testing is a managed pool of freelancers used by Google, Meta, Microsoft, and other world-beating software companies.
-
1
A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.
-
2
IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support... -
3
Baya - SoC Integration Platform
Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity... -
4
UMHDL
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So... -
Crowdtesting That Delivers | TesteumTesteum connects your software, app, or website to a worldwide network of testers, delivering detailed feedback in under 48 hours. Ensure functionality and refine UX on real devices, all at a fraction of traditional costs. Trusted by startups and enterprises alike, our platform streamlines quality assurance with actionable insights. Click to perfect your product now.
-
5
Estimate
Web based Cost Estimation, Material Takeoff and Reconciliation Tool
"Estimate" is an Open Source web based Construction Cost Estimating Software designed for medium and large Civil Construction and EPC (Engineering Procurement and Construction) companies. Features include Management of Schedule of Rates, Analysis of Rates, Project Estimation (Definitive and Control), Tender Evaluation, Cost Sheet preparation, BOQ Generation, Audit and Projection. Estimate is suitable for a wide variety of trades and businesses, including but not limited to:... -
6
rxWebSocket
rxWebSocket is a simple reactive extension of OkHttp Websocket
rxWebSocket is a simple reactive extension of OkHttp Websocket interface with support for Convertor Factories and Interceptors. -
7
Wheefun Computer Prototyping Kit
A Toolkit for Designing Computers
This package is designed for people who are a) interested in writing emulators or b) integrating this level of detain into their applications (e.g., a video game). The ability to do this is useful because a) it allows for tinkering far before physical implementation of the design is. In addition to a strong core, WFCPK will also include modules emulating various processors (e.g., the MOS 6502 and the Zilog Z80) as well as the Video-Audio Interface (a custom VGA-compatible display and... -
8
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
-
9
zamiaCAD is a modular and extensible platform for HW design, analysis, and research. It translates a HW description (VHDL or Verilog) into a language independent IG structure. Applications like a simulator and an eclipse GUI build on top of the IG.
-
Sales CRM and Pipeline Management Software | PipedrivePipedrive’s simple interface empowers salespeople to streamline workflows and unite sales tasks in one workspace. Unlock instant sales insights with Pipedrive’s visual sales pipeline and fine-tune your strategy with robust reporting features and a personalized AI Sales Assistant.
-
10
bel_fft
FFT co-processor in Verilog based on the KISS FFT
... and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1. -
11
RDFConvert
commandline syntax convertor for RDF
RDFConvert is a simple command-line tool for converting RDF file betweeen different syntax formats. It is based on the OpenRDF Rio parser toolkit, and currently supports RDF/XML, Trig, Trix, Turtle, N3, N-Triples, RDF/JSON, JSON-LD, Sesame Binary RDF and N-Quads. -
12
Label2Cue Convertor
converts Audacity label files to .cue (CUE) files
A small Java tool that converts Audacity label files (text format) to standardized .cue CUE Label files. Useful for compatibility with CD burning software, other audio editing software, etc. -
13
PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic... -
14
openAut
Open Source Hardware For Industrial Automation
This project is aimed at producing open source hardware for real time use in industrial automation. This project will have a few sub-projects that will focus on individual hardware for various industrial purpose. Some of the sub-projects will be of type Field-IO Modules development, Analog-IO Module development etc. -
15
BlueSVEP
Bluespec SystemVerilog Eclipse Plugin
BlueSVEP is an Eclipse-based IDE for Bluespec SystemVerilog, a functional hardware description language based on a synthesizable subset of Haskell and SystemVerilog. -
16
VHDT
VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation. -
17
Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
-
18
Application de fines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
-
19
A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.
-
20
vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
-
21
This project includes a set of tools and guidelines designed for rapid production of large-scale embedded systems projects. The tools enable quick generation of reusable, reconfigurable hardware, using a user-specified hardware description language.
-
22
This Eclipse Plugin invoke Simulation, Synthesis and Place&Route tools from various Vendors for HDL (VHDL/Verilog) development.
-
23
A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
-
24
Custom Architecture Generator Tool is a software based on the Netbeans Platform, the main purpose is to accelerate the embedded system realisation with a high level description: VHDL code,C2VHDL conversion,Quartus project generation,real time application
-
25
