Search Results for "state machine"
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Showing 2 open source projects for "state machine"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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MachDB is machine database to catalog of the changing state of your hosts. It consists of a database, an aggregator, an XML spec and some example information gathering scripts. Along with a Web UI, these form the basis of a system that will allow you to
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