Search Results for "state machine"

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Showing 4 open source projects for "state machine"

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  • 1

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 2 This Week
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  • 2

    PerlSCAP

    Perl implementation of a SCAP benchmark tool

    Interprets XCCDF checklists referencing OVAL machine checks and uses them to determine a machine's benchmark state. A XCCDF results file is generated as output.
    Downloads: 0 This Week
    Last Update:
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  • 3
    Meta Menu provides a generalized state-machine approach to making menu-based systems. A given application need only provide a set of states in the form of perl packaged objects and Meta Menu will provide all necessary I/O services, state transitions, et
    Downloads: 0 This Week
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  • 4
    MachDB is machine database to catalog of the changing state of your hosts. It consists of a database, an aggregator, an XML spec and some example information gathering scripts. Along with a Web UI, these form the basis of a system that will allow you to
    Downloads: 0 This Week
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