Search Results for "design"

UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It is a descendant of the popular openwince JTAG tools with a lot of additional features and enhancements.

This is a small library that allows comunicating with a Webasto (tm) W-Bus capable car heating system. Runs on Personal Computers or for embedded devices (slim design). Easily portable. Includes a Heater manager, heater controller program and more. The GIT repository (CVS is deprecated) also includes a control unit application to control W-Bus capable devices, a W-Bus compatible heater unit firmware application and a heater simulator for testing purposes. Also, a serial port loop back driver for linux is included to simulate OBD II K-Line adapters.

JNode is a Java New Operating system Design Effort. JNode is a simple to use and install Java operating system for personal use on modern devices. Any java application runs on it, fast and safe. See our homepage for additional information.

An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the...

We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. To the best of our knowledge, this is the first open-source library of approximate adders that facilitates reproducible comparisons and further research and development in this direction across various layers of design abstraction. This work is a result of collaborative effort between Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany and Vision Image and Signal Processing (VISpro) Lab at SEECS-NUST, Pakistan.

Software and Arduino shield design for a Serial-to-HID device such that old serial gaming devices can be used as USB Hid devices, particularly the SpaceOrb360 and Spaceball 3d CAD devices.

OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.

A Verilog design for a simple ASIC that executes the Ray Tracing Algorithm.

HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.

The goal of zAutomation project is to design/implement hardware, firmware and software for remote control and monitoring of physical objects, by using the ZigBee technology and internet. The field of application is robotics and domotics.

Generic packet visualization tool for generating flow diagrams from formatted logs. Can be used for cache coherency diagrams, software interaction diagrams or to plot network communications.

unPIC is a Perl script that disassembles Microchip microcontroller's HEX files. This is a powerful tool for all reverse engeneers that creates a well understandable assembly source from a binary file. Creates xrefs, labels, subroutines and much more...

The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.

This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.

"DSO" is a Digital Signal Oscilloscope. My DSO will be connected via the USB to the PC. All software to operate the DSO is developed within this project.

CONECT is a software to design, setup, commission and test home and building-automation systems. It will support various bus systems such as EIB.

SHELLEY Software HardwarE Light LanguagE Yep !

Toolkit (.NET/Mono) + GUI (GTK#) to administer and control a Conexant Encore ADSL Modem. Its modular design allows to be extended to support other brands/models.