Search Results for "edif"

...TincrIO comprises a set of commands for pulling design and device data out of the Vivado sandbox into a open, parsable format. With TincrIO, users are able to generate XDLRC device descriptions and export designs out of Vivado into a "checkpoint" of EDIF and constraint files. Beta support is also provided for importing these checkpoints into Vivado. Tincr's source has been moved to GitHub: https://github.com/byuccl/tincr

An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.

An Electronic Definition Interchange Format (EDIF) parser which allows exports from one EDA schematic capture system (such as OrCad) for import into another (such as KiCad)

Framework for the Analysis and Modification of EDIF netlists (FAME) is a C++ framework, developed at Politecnico di Torino, aimed at automating the analysis and modification of complex circuit netlists described in the standard EDIF 2.0.0 language.

This is a formal equivalence checking tool developed @ IIT Guwahati which can be used to verify functional equivalence between circuits (combinational and sequential) of the formats BLIF, verilog and EDIF.

DGC is a tool for the creation of digital netlists. DGC does an optimization and technology mapping for an abstract description of boolean functions and state machines. Output formats are EDIF, XNF and VHDL. Input formats are KISS, PLA and others. See also: http://gitorious.org/dgc-gtk/