Search Results for "c-bus" - Page 5
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Showing 245 open source projects for "c-bus"
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Framework for the Analysis and Modification of EDIF netlists (FAME) is a C++ framework, developed at Politecnico di Torino, aimed at automating the analysis and modification of complex circuit netlists described in the standard EDIF 2.0.0 language.
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This is a Traffic Light with capability of controlling 4 sets of Lamps and Passengers light with one Counter and LCD for displaying the Time for every set of red light.
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'atlc' is a CAD package used for analysing and desiging electrical transmission lines of arbitrary cross section. Also for the design of directonal couplers. Some parts are CPU intensive, so multiple CPUs are supported.
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Program Avr Linux Manager, to prosty interfejs dla programów avr-gcc oraz avrdude. Umożliwia łatwą kompilację i programowanie mikrokontrolerów.
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ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.
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This is a simple viewer for the ``Stream Format'' for CALMA GDSII CAD libraries (``GDS II'', ``.gds'' or ``.sf'') with a couple of limitations. The main functionality is viewing the library layers with different colors.
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These classes are useful for signal processing in Matlab or C++. They bring together tools and methods which may be used interchangeably for Matlab and C++. Their initial use is in conjunction with work towards my degree at UC Berkeley.
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This project has been abandoned. Please go to https://github.com/xesscorp for current open source offerings from XESS Corp.
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Gnetman is primarily a netlist translator, capable of translating between formats such as VHDL, Verilog, and SPICE. Only structural gate-level netlists are supported. Various netlist manipulations are supported.
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The only software you need to increase cash flow, optimize resource utilization, and take control of your assets and inventory.
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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
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Digital Signal Processing Block Diagram Compiler - user extendable to all DSP's, but presently supports only the TI C2000 family. Rich support for fixed point arithmetic, both saturated and unsaturated. Block diagram entry is via TinyCAD (included).
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Lossi (LOgikSchaltungsSImulator - german for "logic circuit simulator"). It simulates logic circuits. Really.
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Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
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GEZEL is a cycle-based hardware description language. The GEZEL tools offer stand-alone - and cosimulation, and code-generation into VHDL code. User-defined library-block extensions in C++ allow to add new cosimulation/cosynthesis interfaces.
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LSim is a software for simulation and make executables to ARM Cortex-M3 mcu from logic gates diagram. LSim can compile logic gates diagram and generate binary executable files (*.bin, *.hex) for cortex-m3 mcu´s (LPC1768, under development).
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pgmtokicad is a project that aims to develop and maintain applications that can be useful for importing custom images in both schematics and printed circuit boards made with KiCAD
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Liquid PCB is a Computer Aided Design (CAD) application for designing Printed Circuit Boards. It is unlike any PCB CAD package you have used before. It has innovative user interface, and lets you create freeform tracks without any straight lines.
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Visualization of PCB (printed circuit board) descriptions in Gerber RS-274X format. The intention is to let a PCB designer take an RS-274X formatted file and generate a 3D concept view, either locally, or generated as PNG/clip, or browsable X3D/VRML.
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IMPORTANT: The flosslogic project has merged with the sigrok project. Development continues in the sigrok wiki, mailing lists, IRC channel, and git repository.
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Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.
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This a print circuit board editor written in Qt. It aims to provide sprint layout like functionalities. It is not actually fonctional at this time, even as an alpha release but I will update my work regularly.
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This project is a collection of tools that are useful for someone working in the computer engineering field. So far this program is able to do logic minimization using the Quine-McClusky Method, numeric base conversion, and some bit manipulations.
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Audacity-Extra
dark themed version of free Audacity sound editor
audacity-extra now provides a sleek dark themed version of the Audacity open source sound editor. The project experiments with Audacity variations. There's a vowel-sound target-practice display for language learners and an analog waveform data logger for embedded systems. -
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It is an 8085 simulator. it is having very user friendly graphical user interface. It can be used to test 8085 programs before actualy implementing them on target board. For Win32 version you must have latest GTK+ runtime installed on your system. Find l