Open Source VHDL/Verilog Electronic Design Automation (EDA) Software

VHDL/Verilog Electronic Design Automation (EDA) Software

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Browse free open source VHDL/Verilog Electronic Design Automation (EDA) Software and projects below. Use the toggles on the left to filter open source VHDL/Verilog Electronic Design Automation (EDA) Software by OS, license, language, programming language, and project status.

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  • 1
    Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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    Downloads: 160 This Week
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  • 2
    adms
    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
    Downloads: 11 This Week
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  • 3
    Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.
    Downloads: 4 This Week
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  • 4

    ghdl-updates

    GHDL - a VHDL simulator

    GHDL is the leading open source VHDL simulator. *** Now on github.com/tgingold/ghdl *** We have binary distributions for Debian Linux, Mac OSX and Windows. On other systems, getting GHDL from here means downloading the current source package and building GHDL from source. Alternatively you can get the latest source version (warning : occasionally unstable!) by pulling a snapshot from the git repository.
    Downloads: 1 This Week
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  • 5
    VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book
    Downloads: 2 This Week
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  • 6
    FSMDesigner
    FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
    Downloads: 1 This Week
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  • 7

    lpACLib

    An Open-Source Library for Low-Power Approximate Computing Modules

    The “lpACLib” library contains the VHDL description of accurate and approximate versions of several arithmetic modules (like adders and multiplier of different bit-widths) and accelerators. Moreover, it also provides the corresponding software behavioral models/implementations developed in C and MATLAB to enable quality characterization. Besides our novel designs, it also contains implementations for several state-of-the-art arithmetic modules and their approximate versions. This open-source library facilitates research and development in approximate computing at higher abstraction levels, and to facilitate reproducible research and comparisons. In case of usage, please refer to our publication: Muhammad Shafique, Rehan Hafiz, Semeen Rehman, Walaa El-Harouni, Jörg Henkel, "Cross-Layer Approximate Computing: From Logic to Architectures", Design Automation Conference (DAC), 2016. Contributors: Authors, Vanshika Baoni, M. Abdullah Hanif http://ces.itec.kit.edu/lpACLib.php
    Downloads: 1 This Week
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  • 8

    ApproxAdderLib

    Library of Approximate Adders

    We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. To the best of our knowledge, this is the first open-source library of approximate adders that facilitates reproducible comparisons and further research and development in this direction across various layers of design abstraction. This work is a result of collaborative effort between Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany and Vision Image and Signal Processing (VISpro) Lab at SEECS-NUST, Pakistan.
    Downloads: 0 This Week
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  • 9
    CoreTML framework
    CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
    Downloads: 0 This Week
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  • 10
    A collection of useful software packages to perform engineering tasks, especially electrical engineering and chip design. All packages come as shrink-wrapped installers for Apple's Mac OS X.
    Downloads: 0 This Week
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  • 11
    Automatic build management for VHDL and Verilog projects. The automatic dependency resolver finds the exact subset of sources, and the correct order they must appear in required to build a project. A Makefile automates the actual build itself.
    Downloads: 0 This Week
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  • 12
    FPGA coprocessor floating point math lib
    libhdlfltp is a VHDL library of floating point operators, all of which are parametrized, synthesizable to FPGAs and cover a number of the core operators in math.h.
    Downloads: 0 This Week
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  • 13
    FT-81M

    FT-81M

    Student Project

    Student Project
    Downloads: 0 This Week
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  • 14
    Platform for advanced open source IP-Core development, i. e. dynamic memory controllers for FPGAs.
    Downloads: 0 This Week
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  • 15
    Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
    Downloads: 0 This Week
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  • 16

    Labcoat: Cleanroom Apps for SuperWikia

    Labcoat; the VHDL graphic emulator.

    Labcoat for SuperWikia Alpha fabrication manages new or revised fabrication processes. Its 'Cleanroom' applets allow codesmiths to access the lab environment, used to create semiconductors, substrate prototypes, chipset instruction blocks and other Labcoat projects. Our extensions in future releases will include UML support for C#/C++ conforming projects, import/export architecture schematics and refactoring sub-projects.
    Downloads: 0 This Week
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  • 17
    Verilog-A Implementation of the Mextram Bipolar Transistor Model
    Downloads: 0 This Week
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  • 18

    NOCEXplore

    Network-on-Chip design exploration tool based on SystemC.

    NOCEXplore is a Network-on-Chip design exploration tool based on SystemC. It includes libraries and executables for easy and fast upgradeable NoC models and a set of shell scripts. The project started during the PhD of Stefano Gigli at DII of Universita' Politecnica delle Marche (http://www.dii.univpm.it/) under the supervision of Prof. Massimo Conti and contribution of several students.
    Downloads: 0 This Week
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  • 19
    OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.
    Downloads: 0 This Week
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  • 20
    Design and implementation of silicon and software for baseband processors conforming to IEEE wireless standards. Initial focus on WiMAX and WiFi.
    Downloads: 0 This Week
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  • 21
    A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.
    Downloads: 0 This Week
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  • 22

    PLP

    Powerfull pre-processor

    Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
    Downloads: 0 This Week
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  • 23
    Project 2306 IDE Rad MacOS MCU DeveR

    Project 2306 IDE Rad MacOS MCU DeveR

    Electronic design and programming tools suite like Eagle, MpLab

    Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned Features : Similar with mainstream market tools IDE and GUI Wrapper like : LabView©, Proteus©, MPLab©, Eagle CAD©, Tools Suite for Most Market Microcontroller. Tools suite for Arduino, Pinguino, Pic, AVR, ARM, Basic Stamp, Risc, other platform Fully Integrated IDE. Adobe PDF Help section SQL Connectivity Community Avail : https://www.facebook.com/Project-Core-2306-Nextgen-Eda-pcbradide-for-Mcumacoslinuxwindows-138250749681138/?fref=ts
    Downloads: 0 This Week
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  • 24
    Ray Tracing micro-processor RTMP. Features: * Programmable pixel shaders. * SIMD 32-bit ALU. * Hardware support for Octree scene traversal. * Ray intersection cache. * Support for mutiple instances of RTMP working concurrently.
    Downloads: 0 This Week
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  • 25

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 0 This Week
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