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Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
A Hardware/Software Co-Simulation package utilizing TCP/IP networking to allow C and Perl based development simulation environments using Verilog or SystemC hardware models.
toolbox with information and programs for Computer Aided Innovation
The scientific background of Skidbladnir is known as the Theory of Inventive Problem Solving; in English abbreviated as TIPS or TRIZ, in German as TRIS.
a set of free tools and software aimed at design automation. SPICE ( NG-spice )MAGIC XCIRCUIT
Main aim - to automate the layout of clock distribution on a chip, using rotary clock oscilation.
Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav