Search Results for "python::module"
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Showing 4 open source projects for "python::module"
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LEF2Verilog
A perl based program to generate stub verilog from LEF
This program is perl based and generate stud verilog module from LEF Macro. Useful while user need stub verilog for annotation during LEF to OA abstract migration or annotation after GDSII import. -
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Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.
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Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
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Libraries for building tools and scripts for ECAD. Contains physical, circuit and Verilog libraries bolted into the 'carrion' module.
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