IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
PC based Oscilloscope and Spectrum analyzer using sound card
Schematic circuit editor for VLSI and Mixed mode circuit simulation.
Free converters across IP-XACT Verilog VHDL Liberty SystemC
IEC 104 RTU Server Client Simulator Source Code Library Win Linux
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
A logic gate simulator for linux developed with Gtk and python.
Tools and libraries for use with systemc and verilog
Run tasks/tests, get trustworthy pass/fail info rolled up
Verilog Finite State Machine (FSM) Code Generator
RxCalc is a calculator for the analysis of multi-stage receiver.
A Cross Platform and Open Source Electronics Design Automation Suite
Penthode simulates, draw and plot electrical power distributions