Search Results for "gnu compiler codeblocks"

v21.06.012 Complete implementation of iec 104 protocol standard including File transfer. Make your RTU, protocol converter, Gateway, HMI, Data concentrator compatible with iec 104. *Industry Proved * Worldwide Customers Download Evaluation Kit - IEC 104 Development Bundle In the Development Bundle, We included IEC 104 Server & Client Simulator, Windows & Linux...

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So,...

A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.

PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic...

The KontrollerLab is an IDE for developing software for Atmel(r) AVR(c) microcontrollers using the avr-gcc compiler, the uisp and the avrdude upload software.

Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.

s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.

Trident is a high-level language compiler for scientific agorithms written in C that target FPGAs.

vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd

SDL REFLEX is the micro kernel of a real time operating system for the AVR microcontroller family. The kernel is especially designed to implement systems described in SDL – “The Specification and Description Language” . Compiler GNU ANSI-C for AVR v.3.3

Provides a GPL'd test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com, and test reports are collected from that project.

DGC is a tool for the creation of digital netlists. DGC does an optimization and technology mapping for an abstract description of boolean functions and state machines. Output formats are EDIF, XNF and VHDL. Input formats are KISS, PLA and others. See also: http://gitorious.org/dgc-gtk/

XAvrTools is an open source graphical frontend for development with Atmels AVR microcontrollers using the UISP download tool and the AVR-GCC C compiler for LINUX. It is written in C++ using KDevelop and the QT library. It will include a software wizard.

RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.

VHDLC is a VHDL to C++ translator aiming at full VHDL '93 compliance. It provides the translator and supporting VHDL libraries for the target host C++ compiler.

Various scripts for several EDA tools such as: RTL Compiler, spyglass, lec, temposync, etc. Scripts are useful in IC design.