Search Results for "zebra design 3"

This project provides a analog / mixed signal IC schematic capture and layout tool with the accompanying netlisters, simulators, and verification tools.

...Insert new hierarchy 8.b. Remove existing hierarchy 9. Associate the IP-XACT memory maps with the SoC component instances 10. Dump out the C Model for the entire design 11. Glue-Logic insertion 12. Spare port insertion across hierarchies 13. Automatic creation of the top module and it's ports based upon specified rule 14. Creates stub module

Analog Insydes is a Mathematica toolbox for symbolic analysis of analog electronic circuits. This project provides a set of free add-ons to Analog Insydes, including a Java front-end and a native netlister for Cadence's Analog Design Environment (ADE).

PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic...

Includes a signal scaling app, many engineering unit conversion calcs, and a task list pad to keep track of progress or notes.

vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.

Verilog 2005 synthesizable subset parser built on ANTLR framework. 3-nov-2014: latest release here: https://github.com/gburdell/parser

This is an attempt to build an Java GUI for a low cost digital storage oscilosope based on a RS232 interface.

SymtaP is a performance analysis tool to determine the worst case execution time for embedded real time applications.

Java source to C source translator, which allows to write MCU programs in Java. Now AVR are supported, others can be added. Convenient Java methods instead of manual register handling.

Equivalence checking for two netlists of ORCAD schematic designs. Check out whether two netlists may generate the idendical PCB in later design stage, even if they are derived from different design procedures with different part-ref and siganl-name.

Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.

Trident is a high-level language compiler for scientific agorithms written in C that target FPGAs.

The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.

PCB plugin for rat selection. The user supplies a pin list via a text file. The plugin selects the rats which connects the listed pins. This functionality intends to help auto-routing with variable track width. See the web site for more detail.

NecJGui is an antennas design tool, interface for Numerical Electromagnetic Code. It allows easily making NEC input files, and viewing them in 3D. It also contains a version of the simulator, so it's complete IDE for full-wave EM simulation.