11 projects for "c# source code example" with 2 filters applied:

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  • 1
    Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
    Downloads: 0 This Week
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  • 2
    dvkit

    dvkit

    Eclipse-based IDE for design verification tasks

    DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code
    Downloads: 7 This Week
    Last Update:
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  • 3
    Qfsm

    Qfsm

    A graphical Finite State Machine (FSM) designer.

    A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
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    Downloads: 13 This Week
    Last Update:
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  • 4
    CAD2Board

    CAD2Board

    is a Qt program to generate SMD chip shooter code

    Still struggling with Excel to setup your pick and place machine ? Cad2Board reads component mounting information from Eagle, Altium Designer and Mentor Expedition PCB designs. Component or component groups can be assigned to feeder slots by drag and drop. Any modifications for PCB population can be defined to generate PCB variants, consider rotations from unusual tape and reel packaging or to account in advance for CAD library or PCB design bugs. Generated setup data is stored in a...
    Downloads: 0 This Week
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    SIEM | API Security | Log Management Software

    AI-Powered Security and IT Operations Without Compromise.

    Built on the Graylog Platform, Graylog Security is the industry’s best-of-breed threat detection, investigation, and response (TDIR) solution. It simplifies analysts’ day-to-day cybersecurity activities with an unmatched workflow and user experience while simultaneously providing short- and long-term budget flexibility in the form of low total cost of ownership (TCO) that CISOs covet. With Graylog Security, security analysts can:
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  • 5
    Covered
    Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
    Downloads: 13 This Week
    Last Update:
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  • 6
    OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.
    Downloads: 0 This Week
    Last Update:
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  • 7
    s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.
    Downloads: 0 This Week
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  • 8
    Downloads: 0 This Week
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  • 9
    Libraries and sample code for accessing remote toolpath delivery services such as VoluMill. Although much of the code is specific to the VoluMill service, it also defines open standards for exchanging toolpath information, parameters, and geometry.
    Downloads: 0 This Week
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  • 10
    "cif2tribes" is a console-based tool for converting integrated circuit layouts into maps usable in the game Tribes 2, as a 3D visualization aid. The project code is modular enough to be easily extended to different game engines and input file formats.
    Downloads: 0 This Week
    Last Update:
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  • 11
    ESOMA is a component orientated framework for simulation and evaluation of arbitrary microprocessor and DSP architectures. Simulators using ESOMA are runtime configurable. Architectural changes do not need recompiling. Programming language is C++ (Linu
    Downloads: 0 This Week
    Last Update:
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