Search Results for "arduino source code"
Sort By:
36 projects for "arduino source code" with 2 filters applied:
-
Gen AI apps are built with MongoDB AtlasMongoDB Atlas provides built-in vector search and a flexible document model so developers can build, scale, and run gen AI apps without stitching together multiple databases. From LLM integration to semantic search, Atlas simplifies your AI architecture—and it’s free to get started.
-
Keep company data safe with Chrome EnterpriseMake AI work your way with Chrome Enterprise. Block unapproved sites and set custom data controls that align with your company's policies.
-
1
AUDio MEasurement System
PC based Oscilloscope and Spectrum analyzer using sound card
AUDio MEasurement System - a multi-platfrom system for audio measurement through sound card in the PC. It contains: generator, oscilloscope, audio spectrum analyzer (FFT) and frequency sweep plot. Compiles and works under Linux, Windows and MacOS. Source code is available in "git" and as ZIP snapshot. For more information see README.md -
2
myNetPCB
Community driven PCB Layout and Schematic capture software
PCB Layout and Schematic capture tool for Win/Linux/Mac. Source code at https://github.com/sergei-iliev/myNetPCB -
3
eLogSim
Digital circuit simulator
...It uses a test oriented stimulus approach and offers a statistical (or exhaustive if it makes sense) fault simulation option. eLogSim has a simple GUI and is pre-compiled for Ubuntu 20, Mint 20, CentOS 8, openSUSE 15, FreeBSD 12, Solaris 11, Windows 10/11 & Raspbian/Raspberry PiOS Buster (32/64bit) & Ubuntu-MATE 20.04 (64 bit) operating systems. Cross platform & -network, concurrent fault simulation now available. Commented, easy-to-compile source-code included as well. -
4
SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
Our Free Plans just got better! | Auth0You asked, we delivered! Auth0 is excited to expand our Free and Paid plans to include more options so you can focus on building, deploying, and scaling applications without having to worry about your security. Auth0 now, thank yourself later.
-
5
dvkit
Eclipse-based IDE for design verification tasks
DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code -
6
Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
-
7
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
-
8
NetlistViewer
SPICE netlist visualizer
Please go to https://github.com/f18m/netlist-viewer for most updated code -
9
pyGerber2Gcode
Python Gerber to G-code converter
pyGerber2Gcode is a Pyhon based simple Gerber to G-code converter. -
Pest Control Management SoftwareBuilt for the pest control industry, but also works great for Mosquito Control, Bin Cleaning, Window Washing, Solar Panel Cleaning, and other Home Service Businesses in need of an easy-to-use software that helps you simplify routing, scheduling, communications, payment processing, truck tracking, time tracking, and reporting.
-
10
ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
-
11
Project 2306 IDE Rad MacOS MCU DeveR
Electronic design and programming tools suite like Eagle, MpLab
Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned... -
12
GNUSim8085 is a simulator and assembler for the Intel 8085 Microprocessor. For downloading latest release please head to the website - https://gnusim8085.github.io/ For source code - https://github.com/GNUSim8085/GNUSim8085
-
13
PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
14
Cadence 614 Installer
Cadence 614 installing scripts with source files
this code include automation for installing Cadence614 with Calibre2011 all you need to do is to install Centos 6.5 32bit on your machine http://archive.kernel.org/centos-vault/6.5/isos/i386/CentOS-6.5-i386-LiveCD.iso and the scripts will do the rest -
15
Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
16
ApproxAdderLib
Library of Approximate Adders
We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. To the best of our knowledge, this is the first open-source library of approximate adders that facilitates reproducible comparisons and further research and development in this direction across various layers of design abstraction. This work is a result of collaborative effort between Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany and Vision Image and Signal Processing (VISpro) Lab at SEECS-NUST, Pakistan. -
17
STANTOR
Scada for Home Automation
Stantor is a SCADA for home automation/domotic project. It drives : k8061-K8055(USB), K8000(I2C), Arduino Mega and Uno, X10, 1-Wire, electricity meters, Webcam (motion), infrared remote controls. It uses WEB browser, smartphone, xHTML, SOAP, Websocket, HTML5 Apache, mySQL, PHP, javascript and Ajax. Stantor allows control of electrical equipments like boilers, shutters, lamps, pumps, etc...connected to the 220V/110 VAC. Gathering information of various kinds such as temperature, light,... -
18
CAD2Board
is a Qt program to generate SMD chip shooter code
Still struggling with Excel to setup your pick and place machine ? Cad2Board reads component mounting information from Eagle, Altium Designer and Mentor Expedition PCB designs. Component or component groups can be assigned to feeder slots by drag and drop. Any modifications for PCB population can be defined to generate PCB variants, consider rotations from unusual tape and reel packaging or to account in advance for CAD library or PCB design bugs. Generated setup data is stored in a... -
19
ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.
-
20
Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
-
21
vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
-
22
OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.
-
23
s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.
-
24
-
25
Libraries and sample code for accessing remote toolpath delivery services such as VoluMill. Although much of the code is specific to the VoluMill service, it also defines open standards for exchanging toolpath information, parameters, and geometry.
