Search Results for "base-files"
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Showing 67 open source projects for "base-files"
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Managing your therapy and rehab practice is a time-consuming process. You spend hours on paperwork, billing, scheduling, and more. Raintree’s Therapy & Rehab EHR is here to help you manage your practice more efficiently. With our all-in-one solution, you’ll get the tools you need to streamline your therapy and rehab practice, improve patient care, and get back to doing what you love.
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Track all your service data in one easy-to-use system, enabling your team to move faster and generate more revenue for your bottom line.
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Image To Gerber Converter
Convert any image to gerber and drill files
ImageToGerber makes it easy to convert any image to gerber files, ready to send to a PCB manufacturer. More info at: https://www.imagetopcb.com Demo video: https://youtu.be/HUvt0mOHv_M Forget about spending long hours etching and drilling at home, or learning to use complicated CAD software, schematics, layout design,… And more importantly, ImageToPCB is more than just a converter, it expands the potential of your design or image. It unlocks the possibility to easily make... -
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Gerber2PDF
Gerber to PDF converter
Gerber2PDF is a command-line tool to convert Gerber files to PDF for proofing and hobbyist printing purposes. It converts multiple Gerber files at once, placing the resulting layers each on it's own page within the PDF. Each layer has a PDF bookmark for easy reference. Layers can optionally be combined onto a single page and rendered with custom colours and transparency. There is a Drill to Gerber converter available from the downloads page. -
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Kactus2
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Kactus2 is a toolset for IP-XACT based SoC design and provides packaging, integration and configuration of HW and SW components, plus register design and HDL import and generation. The source code is hosted at https://github.com/kactus2/kactus2dev. An example IP library is available at https://github.com/kactus2/ipxactexamplelib Video tutorials are available at https://www.youtube.com/user/Kactus2Tutorial Issue tracker is available at... -
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UMHDL
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So,... -
Drive amazing product experiences with quality product data.
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BuddyCAD
A set of freeware applications for viewing/processing P-CAD files.
BuddyCAD Viewer+ can view/process files for following P-CAD versions: - P-CAD v4.5 - P-CAD v8.5 / v8.7 / v9.0 - P-CAD 99 / Accel / 2002 / 2004 / 2006 (through ASCII import) -
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IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API... -
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Free VHDL Parser with Java, Python and T
IEEE VHDL-93 LRM supported parser implemented in Java, APIs Python/Tcl
This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. This tool has been... -
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jCLS
The Component Library Sorcerer
... the molesting parts of this job. Feature in progress: -Some graphical improvements -Conceptual improvements -Some improvements in the file format Features added in next Release: -Built-in tutorial -Better libraries with library browser -Save and load libraries from a file -Export library data to csv files -Automatic Update Notification -
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simutron
AVR simulator IDE
Electronic circuit simulator. Simple environment to run and debug firmware for AVR 8-bit microprocessors. Able to run arduino firmware. Internally this program uses the open source Simavr AVR Processor Simulator (https://github.com/buserror/simavr) and wraps all its functions in a GUI shell. Setups for firmware debugging scenarios can be created dynamically. Able to run 16MHz MCU with decent set of external parts in real time. In particular this can be used for development of CNC firmware... -
This product is especially great for project managers, COOs, finance professionals, accountants, or payroll admins in any industry.
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Electronic Circuit Optimization
Optimer: a SPICE base electrical/ electronic circuit optimization tool
This project is dedicated to the optimization of (any) electrical and electronic circuits and components using evolutionary and heuristic algorithms incorporated with SPICE simulators (such as HSPICE, ngSPICE, etc.). We provide Optimer, which is a user graphical interface for circuit design and optimization. Website: https://www.circuitoptimization.com/ E-mail: contact@circuitoptimization.com/ -
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Gerbv is an open source Gerber file (RS-274X only) viewer. Gerbv lets you load several files on top of each other, do measurements on the displayed image, etc. Besides viewing Gerbers, you may also view Excellon drill files as well as pick-place file
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SVEditor is an Eclipse-based IDE (Integrated Development Environment) for SystemVerilog and Verilog files. It features syntax coloring, content assist, source indent and auto-indent, and structure display.
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Jumbocad
This is a very powerful Schematic and PCB layout tool for Engineer
This is a very powerful Schematic and PCB layout tool for electronic Engineer. It is very easy to use. Coming version will add the SPICE features as well as the 3D model. This tool is target for single user, so all the things such as Schematic, PCB layout, SPICE model, 3D models are all combined into a single project file "*.prj" in ZIP file format. Anyone should able to explore and see the structure of files using any zip tool. -
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Integrated Circuit Design Software that quickly automates design of analog and digital circuits for use in schematics, device modelling, design re-use, architecture, signal processing and IC manufacture.
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Timing-gen is a Linux tool to generate high quality Postscript timing diagrams from text input files.
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
... and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1. -
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Control Techniques Software
CT Soft is software designed to be used with Control Techniques Drives
CTSoft can be used for configuring the following drives: Digitax ST Base Digitax ST Indexer Digitax ST Plus Digitax ST EZMotion FXMP25 Field Controller Mentor MP Unidrive 'Classic' in open-loop, closed-loop vector and servo modes Unidrive SP open-loop, closed-loop vector servo modes and regen mode Commander SK drives Commander GP20 Drive in open-loop, closed-loop vector Unidrive ES open-loop, closed-loop vector and servo modes Unidrive PV CTSoft system requirements: Pentium IV... -
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dxf2pcb
Convert DXF drawings of circuit boards to gEDA-PCB files.
This Python script reads in a DXF (ascii) file and generates a PCB output compatible with PCB Designer, part of the gEDA suite. It is designed for two purposes: One is to generate a PCB snippet from a mechanical drawing (such as a board outline), the other is to produce element files from CAD drawings. PCB snippets are easily imported into an existing gEDA-PCB project using File -> Load Layout to Buffer. Generated element files are ready to use (except for special cases like no-paste flags... -
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openCarac
openCarac : Automatize your Spice simulator runnings
openCarac aims to automatize the characterization of electronic circuits using your favourite Spice simulator and provide output files in HTML, LaTeX (c) and GNU Octave (c) scripts. openCarac is natively compatible with various simulators including: - Ngspice (c), http://ngspice.sourceforge.net - Gnucap (c), http://gnucap.org/dokuwiki/doku.php?id=gnucap:start - Xyce (c), http://xyce.sandia.gov It comes with an API which permits to add other features and extend openCarac compatibility... -
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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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Cadence 614 Installer
Cadence 614 installing scripts with source files
this code include automation for installing Cadence614 with Calibre2011 all you need to do is to install Centos 6.5 32bit on your machine http://archive.kernel.org/centos-vault/6.5/isos/i386/CentOS-6.5-i386-LiveCD.iso and the scripts will do the rest -
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic... -
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qtwavetool
Open Teradyne wave files (.wav)
Tool to open Teradyne ATE .wav files and view content in tabular form or plot and view graphically.