Search Results for "base-files"
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Showing 29 open source projects for "base-files"
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Image To Gerber Converter
Convert any image to gerber and drill files
ImageToGerber makes it easy to convert any image to gerber files, ready to send to a PCB manufacturer. More info at: https://www.imagetopcb.com Demo video: https://youtu.be/HUvt0mOHv_M Forget about spending long hours etching and drilling at home, or learning to use complicated CAD software, schematics, layout design,… And more importantly, ImageToPCB is more than just a converter, it expands the potential of your design or image. It unlocks the possibility to easily make... -
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UMHDL
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So,... -
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Free VHDL Parser with Java, Python and T
IEEE VHDL-93 LRM supported parser implemented in Java, APIs Python/Tcl
This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. This tool has been... -
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jCLS
The Component Library Sorcerer
... the molesting parts of this job. Feature in progress: -Some graphical improvements -Conceptual improvements -Some improvements in the file format Features added in next Release: -Built-in tutorial -Better libraries with library browser -Save and load libraries from a file -Export library data to csv files -Automatic Update Notification -
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SVEditor is an Eclipse-based IDE (Integrated Development Environment) for SystemVerilog and Verilog files. It features syntax coloring, content assist, source indent and auto-indent, and structure display.
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Timing-gen is a Linux tool to generate high quality Postscript timing diagrams from text input files.
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
... and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1. -
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dxf2pcb
Convert DXF drawings of circuit boards to gEDA-PCB files.
This Python script reads in a DXF (ascii) file and generates a PCB output compatible with PCB Designer, part of the gEDA suite. It is designed for two purposes: One is to generate a PCB snippet from a mechanical drawing (such as a board outline), the other is to produce element files from CAD drawings. PCB snippets are easily imported into an existing gEDA-PCB project using File -> Load Layout to Buffer. Generated element files are ready to use (except for special cases like no-paste flags... -
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic... -
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PCBColorizer
Automatic coloring PCB - make a color circuit board for installation.
The program is designed for automatic coloring schemes of printed circuit boards for ease of installation. For its work requires some files with information on the printed circuit board, package generated by P-CAD. The basic principle: each type of component (identical components) are marked with a unique symbol that has its own color and style. This simplifies the visual search component on the board. The program also generates a text list of components, where the marks, what type... -
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A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), OpenAccess, DXF, CIF (Caltech Intermediate Form), ...
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A Step Closer to a Fully Gui ATLAS .log Converter A Gui .in Editor to be Used by ATLAS .log awk converter
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This program provides for easy modification and viewing of SPICE circuit files. It will also read SPICE3 RAW format (as well as GnuCap) and create graphs of results through an interactive GUI. It supports waveform math, copying to clipboard, and saving.
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Verilog 2005 synthesizable subset parser built on ANTLR framework. 3-nov-2014: latest release here: https://github.com/gburdell/parser
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This project is a collection of tools that are useful for someone working in the computer engineering field. So far this program is able to do logic minimization using the Quine-McClusky Method, numeric base conversion, and some bit manipulations.
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The project has moved! see http://code.google.com/p/kicadocaml/ Kicadocaml is a small project that reads and writes Kicad board (*.brd) files produced by Kicad's pcbnew software. Currently, the software consists of an OpenGL gui & a tool to allow ar
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PyPCB is a Python package for working with PCB (http://pcb.sourceforge.net) files. PyPCB can be used to create new useful tools, as footprint generators or library managers.
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GBTiler, a Gerber circuit board tiling program allows engineers, electronics hobbyists and other users with Gerber RS274X format files to "tile" or combine separate Gerber files -- circuit boards -- into a single, valid Gerber formatted file.
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Laboratory Circuit Simulator is transient simulator whiht analog and digital components support for laboratory classes. This support spice netlist files, DSP Tms320f243 DSPemu integration and has high customizable device modules development in c.
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XML is one way to transfer a Printed Circuit Board (PCB) data base between Software Applications. This projects starts with an export from PCB123 and creates a Kicad brd file.
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libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.
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unPIC is a Perl script that disassembles Microchip microcontroller's HEX files. This is a powerful tool for all reverse engeneers that creates a well understandable assembly source from a binary file. Creates xrefs, labels, subroutines and much more...