Search Results for "c-bus" - Page 14
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Showing 400 open source projects for "c-bus"
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Production (3 level) Programmer for Microchip PIC on Win9X,DOS,NT,Win2K. Flash and Eprom, 14 and 12 bit devices. Printer Port programmers and the BEL In-circuit Dual PRODUCTION Pic Programmer board.
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"DSO" is a Digital Signal Oscilloscope. My DSO will be connected via the USB to the PC. All software to operate the DSO is developed within this project.
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Decodify is a simple program that parses a numerical string and extracts different parts of it as per user query. The main application of 'decodify' is to extract parts of a control bus in logic simulation, but many other uses are possible.
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Portatux is an interactive ncurses interface as well as a command line tool for controlling the 8 data pins in the parallel port in Linux and FreeBSD.
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The XML PCB Renderer is an application which takes an XML definition of a printed circuit board (consisting of pads, tracks and components) and renders it to a PNG file suitable for printing onto paper or transparency ready for UV exposure.
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Parallel Port Eprom Programmer contains a GNU/Linux driver that controls the eprom programmer throught the parallel port and a tool which allows reading and writing eproms.
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asfpga is an assembler written for use in FPGA design. It can be easily modified for your instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set. The current version al
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Two dimensional (2D) fine mesh finite element (FE) grid editing system. Includes constrained Delaunay triangulation, and automated grid resolution changes based on local attributes. Win32 and Motif GUIs. Mature application, now going open source.
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The Verilog Construction Toolkit is a C++ library which provides the ability to read in, create and or modify verilog cell-based structural netlists.
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The Octtools, a CAD system to promote research and education in microelectronics developed by Berkeley. Includes synthesis, placement and routing tools. Current development aims towards utilising current process technologies.
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a set of free tools and software aimed at design automation. SPICE ( NG-spice )MAGIC XCIRCUIT Main aim - to automate the layout of clock distribution on a chip, using rotary clock oscilation.
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Experimental Boundary Scan (EBS) project provides software (driver + application) support to JTAG/IEEE 1149.1 boundary scan master (BSM) controllers under the Linux OS.
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Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav
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Virtual electronic circuit simulation with JAVA based schematic entry and wave viewer, based on (Berkeley) SPICE, for any OS/Server/Browser configuration. Due to missing public feedback for over one year its status is set to INACTIVE (1/2004) - sorry.
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HSP16 is a Pesona-16 (http://www.mysem.com) microprocessor simulation and development environment written in C. HSP16 is capable to simulate and run unmodified Pesona-16 assembly.
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This program is a simulator/debugger for Atmel AVR flash microcontrollers, built with Motif (incompatible with Less Tiff). It has language independent interface. This version can almost fully simulates AT90S and ATmega series.
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This is a Computer Aided Electronic Design tool. It features schematic capture, simulation and PCB layout for both analog and numerical componants with the help of Gnome.
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PROJECT IS DISCUNTINUED This project is about to contain information how to write data like boot loader into various flash devices on diffrent CPUs trough JTAG interface
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This is an IEEE 1532 compliant JTAG programmer for CPLDs, FPGAs and similar programmable logic devices. It is only starting; developers are welcome!
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Transcalc is an analysis and synthesis tool for calculating the electrical and physical properties of different kinds of RF and microwave transmission lines. Transcalc is built using the GIMP toolkit (GTK+) for its GUI interface.
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Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.