Search Results for "verilog compiler"
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Showing 26 open source projects for "verilog compiler"
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Clash
Haskell to VHDL/Verilog/SystemVerilog compiler
Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. It provides a familiar structural design approach to both combinational and synchronous sequential circuits. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog. Clash is an open-source project, licensed under the permissive BSD2 license, and actively maintained by QBayLogic. The Clash project is a Haskell Foundation affiliated project. Clash is built on Haskell which provides an excellent foundation for well-typed code. ... -
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XLS
XLS: Accelerated HW Synthesis
XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA/ASIC flows. ... -
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a... -
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BSC
Bluespec Compiler (BSC)
BSC is the open source compiler toolchain for Bluespec SystemVerilog, a high-level, rule-based hardware design language. It translates Bluespec descriptions into synthesizable Verilog, letting developers bring typed, modular abstractions into mainstream FPGA/ASIC flows. The compiler performs scheduling of atomic rules, elaborates parameterized modules, and enforces interface contracts, producing predictable RTL that integrates with existing EDA tools. -
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AWS EC2 FPGA
AWS EC2 FPGA hardware and software development Kit
...After creating an FPGA design (also called CL - Custom logic), developers can create an Amazon FPGA Image (AFI) and easily deploy it to an F1 instance. AFIs are reusable, shareable and can be deployed in a scalable and secure way. Development experience leverages an optimized compiler to allow easy new accelerator development or migration of existing C/C++/openCL, Verilog/VHDL to AWS FPGA instances. Fully custom hardware development experience provides hardware developers with the tools required for developing AFIs for AWS FPGA instances. -
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Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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UMHDL
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So,... -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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JavaRock is a project to develop a compiler from java to vhdl, which enables hardware design by java. Developping JavaRock is over, and the project continues in Synthesijer http://synthesijer.sourceforge.net . Like JavaRock, Synthesijer also aims to develop a compiler from Java to VHDL, which enables hardware design by Java. In addition, Synthesijer generates Verilog HDL and aims to implement advanced features such as optimization, graphical tools, and so on.
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BlueSVEP
Bluespec SystemVerilog Eclipse Plugin
BlueSVEP is an Eclipse-based IDE for Bluespec SystemVerilog, a functional hardware description language based on a synthesizable subset of Haskell and SystemVerilog. -
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OpenShader
Open architecture GPU simulator and implementation
Documentation, simulator, compiler, and Verilog implementation of a completely open-architecture graphics processing unit. This design is intended for academic and commercial purposes. The first step is to develop a detailed GPU simulator and compiler. The second step is to implement the GPU in synthesizable Verilog. The third step is to develop a feedback loop between the simulator and implementation, allowing power, performance, and reliability aspects of the hardware to feed back into ever more detailed and accurate simulations of a complete GPU. ... -
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Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
...Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation) -
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A compiled logic verilog compiler/simulator for pipelined verilog designs. The simulator can simulate n copies of the verilog where n is the width of integers on the machine that it runs on, simultaneously.
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FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info in wiki.
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Endit is a text editor mean to HDL source code writing and hacking, like Verilog and VHDL. It integrated a open source verilog compiler , Icarus verilog compiler, in it which is also an excellent open source verilog compiler.
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MPC, The Multi Purpose structural Compiler is a tool for generation of network descriptions in various formats or languages (VHDL/Verilog/..), from an efficient structural description language.
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Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
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A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
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gscc stands for GNU SystemC Compiler Collection, witch is a set of tools to manipulate systemc code ( systemc is a hardware description language www.systemc.org ). The most notable tool is called gsc, witch is a systemc to verilog translator.
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Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.
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vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd
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Provides a GPL'd test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com, and test reports are collected from that project.
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RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.
