Search Results for "c to verilog" - Page 5
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Showing 137 open source projects for "c to verilog"
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HdlEdit is a graphical design entry tool for VHDL and verilog. It's GUI is based on the FOX project. So both platforms linux and windows will be supported. Design entry could be done via block diagrams, flow charts and truth tables.
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vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd
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The SBus is a family of high-speed packet-based databus standards, suitable for both networking and interdevice communication. They are optimized for high data density transactions. This project creates and documents the standards, schematics, and driver
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the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol
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A CRM and Sales Data Management Platform for Multi-Line Sales TeamsRepfabric is a customer relationship management (CRM) software designed specifically for multi-line sales teams (i.e. reps, distributors, wholesalers, dealers, and manufacturers). It streamlines and simplifies the sales process by providing deep integration with email, contacts, calendars, and deal tracking. The platform enables users to track commissions from CRM to sale, make updates directly from mobile devices, and document sales calls using voice-to-text features.
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A collection of useful software packages to perform engineering tasks, especially electrical engineering and chip design. All packages come as shrink-wrapped installers for Apple's Mac OS X.
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This project is a collection of Open Source crypto cores and implementations relating to high speed cryptanalysis/cracking and complex implementations.
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This project is developed for Full Customer Design Enviroment. Schematic Entry/SPICE/SPICE(RF)/Layout/Verilog-AMS Via /Verilog Via Will be included.
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produce full software package using the binary decision diagram (BDD) representation to manipulate logic maps for design optimization objectives multiplyer{like(A+B)(C)(D)}In C++ Core.C++ GUI.VB6 Verilog Modules Quin McCluskey Multi Functions Operations
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m4-la is a Logic Analyzer written in VHDL for the Xilinx ML403 Development board featuring the Virtex4 FPGA. The user interface is written in C for Windows32 based platforms. Xilinx ISE and EDK tools compile the VHDL and MS Visual Studio compiles the UI.
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HR Onboarding SoftwareWorkBright is a cloud-based new hire onboarding solution that provides assistance for the processing and induction of new employees before their first day on the job. Simple and easy-to-use, this paperless digital onboarding platform enables new employees to upload photos of relevant documents, fill out their W4s, capture signatures electronically, and complete all paperwork from their tablets, laptops, or smartphones. With WorkBright, organizations can seamlessly eliminate manual data entry, streamline the form correction workflow efficiently, deliver automated reminders, and more.
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A Hardware/Software Co-Simulation package utilizing TCP/IP networking to allow C and Perl based development simulation environments using Verilog or SystemC hardware models.
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Veri-indent is a verilog source code Parser,Analyzer and Beautifier. (similar to c 'indent' , but more than that). Verilog source can be formatted and Symbol table, list of registers,wires,pli calls in source code can be extracted.
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A software package that will combine different embedded computing platforms with home exercise equipment and a Qt client program in order to provide tracking of health and exercise performance.
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The Affordable BIOS Restoration Tool provides VHDL and C code to recover from failed BIOS upgrades using affordable CPLD's. EEPROM's and Flash chips can be restored with this flash programmer. Interfaces for DIP and tsop packages are being developed.
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The Verilog Construction Toolkit is a C++ library which provides the ability to read in, create and or modify verilog cell-based structural netlists.
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RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.
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Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav
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Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
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Libraries for building tools and scripts for ECAD. Contains physical, circuit and Verilog libraries bolted into the 'carrion' module.
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Oscilloscope set top box for PC. There are many projects like that, but we want to try to design it in our way.