Search Results for "fpga" - Page 2
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Showing 159 open source projects for "fpga"
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Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.
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OpenOK 2
OpenOK Fork
An open library for interfacing the Opal Kelly brand FPGA development boards. Dowload Here: https://github.com/JorgeFrancisco/OpenOK_2 -
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Uart32
Win32 API wrappers for accessing COM Uart in blocking mode
Uart32 is a C++ wrapper around the win32 Serial Port API that allows blocking-mode access to the COM port. This library works great for accessing a UART serial port from a background worker thread. It features: a simple c++ class. (temporarily removed for maintainance. Use DLL API Instead) built in per access timeout on data receive. a C-API wrapper that is exportable to C# DLL import class -
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BFGminer
Miner for Bitcoins
BFGMiner is a modular ASIC/FPGA miner written in C, featuring dynamic clocking, monitoring, and remote interface capabilities. Bitcoin miner software with multi-threaded multi-pool gpu, fpga and asic mining support. Bitcoins are a digital currency, exchanged freely against all other currencies. coins may be issued by everyone, one just needs considerable computer power - and luck. to even out rewards for one's contribution, many initiative have forms to provide pools of computers and share... -
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ipdbg
IPDBG are free tools to debug intellectual properties (IP cores).
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can4linux
CAN bus device driver
can4linux is hosted on https://gitlab.com/hjoertel/can4linux since 2016. Don't use SourceForge anymore for this code. can4linux is an universal Linux device driver for ISA or PCI interface boards with CAN interface and embedded CAN controller solutions. Based on the API provided by can4linux commercial protocol stacks for CANopen, J1939 and DeviceNet are available. A first PCI board with an FPGA based CAN FD controller is supported (TARGET=IXXAT_IB500) in the CAN FD ISO mode but also non... -
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LArIAT FPGA Trigger
Firmware (VHDL source) for the CAEN V1495 board
This is the source for a customized firmware that runs on the Altera Cyclone I FPGA mounted on a CAEN V1495 VME board. It was written in support of the LArIAT - Liquid Argon in The trigger module takes 16 ECL/LVDS inputs, in our case from various beamline counters. It has a custom firmware which looks for user programmable patterns corresponding to “good” events. A good pattern results in a fast trigger output and starts a clock. The clock counts for the maximum drift time in the TPC... -
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Sercos SoftMaster
Software-based Sercos Industrial Ethernet Master
The Sercos SoftMaster is intended for implementing a software-based Sercos Industrial Ethernet master on industrial automation controllers. It can be used with controllers that do not provide a dedicated Sercos III master hardware like the Sercos master IP core running on an FPGA. The SoftMaster may be used with a standard Ethernet hardware such as a standard PCI / PCI express Ethernet controller in order to implement a Sercos III master interface. The Sercos Softmaster Core is entirely... -
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SOCGEN is a collection of tools that will help create digital components/ip_cores and then integrate them into a "System on a Chip"(SOC) for use in ASIC or FPGA designs.
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RPTParse
Quartus project compilation reports parsing tool
Altera Quartus creates .rpt files during synthesis, place&route and bitstream generation stages of FPGA project compilation. Verification engineer checks these reports, finds warning messages and put them into own report. But big projects can contain a lot of warnings, and manual warning search is very boring and long process. That's why this parsing tool was created. This software parse report file, classifies warning types and place them into own report, where types of warnings and their row... -
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phase_lock
Arduino/FPGA signal processing
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QNICE is a simple 16 bit processor intended to teach the basics of hardware design as well as operating system design. A TTL implementation is planned, a FPGA implementation is available here: http://qnice-fpga.com. Currently there exists a C based simulator and an assembler.
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An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views...
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AS2CBench
Accelerated S2CBench benchmarks
Accelerated version of the Synthesizable SystemC benchmark suite (S2CBench), mapped onto Terasic's DE1-SoC FPGA board. Testbench runs on the ARM Cortex-A processor DUT is mapped onto the programmable logic. -
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FPGA remote lab
Laboratory for remote practices in FPGA devices
The design of an open platform devoted to allow students perform distance practices with a real FPGA device involves both hardware and software components. -
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This (Python) tool allows you to easily create FPGA bitfiles for your embedded system, from several Open Source IPs (compatibles with the OpenCores Wishbone bus) . It will also generates the corresponding drivers (currently only Linux ones).
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MatlabSimulink2CPP
Demo of Simulink to C++ C or HDL FGA for HFT potential
Video and files download for Visual trading idea to C++ or FPGA HFT Meetup File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated) Powerpoint MATLAB SIMULINK http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/ -
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cMIPS
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips The code here is no longer up to date. The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5%... -
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piconf
Processing Instruction Configurator
... Foundation on 19 November 2007. The coding language is C++11 making use of object orientation and polymorphism. It is intended to work on all POSIX-compliant (Linux/BSD/UNIX-like) operating systems and on some embedded devices, e.g., Zynq based devices like the ZedBoard or the MicroZed supporting the AXI interface to communicate between the Processing System (PS) aka CPU and the Programmable Logic (PL) aka FPGA. It consists of two main binaries following a master/slave model. -
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Cgminer
The combined CPU, GPU, FPGA, and ASIC miner for bitcoin, and litecoin
Features: - Very low overhead free c code for Linux and windows with very low non-mining CPU and ram usage - Stratum and GBT pooled mining protocol support, including ultra low overhead solo mining - Scaleable networking scheduler designed to scale to any size hashrate without networking delays yet minimise connection overhead - long poll support - will use longpoll from any pool if primary pool does not support it - Self detection of new blocks with a mini-database for slow/failing... -
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ZTEX MicroBlaze MCS Demo
Demo of MicroBlaze MCS on ZTEX board LCD and USB
MicroBlaze MCS writing strings to LCD and USB. LCD not needed to run the demo. Free webpack license required. MicroBlaze code written in C. -
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CGMiner
ASIC and FPGA miner in C for Bitcoin
CGMiner is an open source graphical frontend for mining Bitcoins. It supports both pooled and solo Bitcoin mining. The miner supports ASIC/FPGA/GPU mining. -
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BitBandit
FPGA Fault Injection Tool Suite
BitBandit is a Fault Injection Tool Suite for the PowerPC 405 on the Xilinx Virtex4 FX60 FPGA. BitBandit enables users to emulate faults in the Processor's general purpose registers, special purpose registers, instruction cache and data cache. This platform was developed as part of an Autonomous, On-board Processing for Sensor Systems (A-OPSS) NASA sponsored Project. This initial code release will provide a basic design for the Xilinx ML410 development board with future releases providing...