LArIAT FPGA Trigger

This is the source for a customized firmware that runs on the Altera Cyclone I FPGA mounted on a CAEN V1495 VME board. It was written in support of the LArIAT - Liquid Argon in

The trigger module takes 16 ECL/LVDS inputs, in our case from various beamline counters. It has a custom firmware which looks for user programmable patterns corresponding to “good” events. A good pattern results in a fast trigger output and starts a clock. The clock counts for the maximum drift time in the TPC (roughly 330 microseconds) and the board then outputs a delayed trigger. The fast output is used to trigger the PMT digitizers while the slow output is used to record the last 330 microseconds from the TPC digitizers. The trigger contains logic to veto on “bad” patterns and inhibit TPC readout if a second good or bad pattern occurs during the drift time.