Search Results for "fpga"

FuseSoC is a package manager and build abstraction tool for hardware description language (HDL) code, aimed at simplifying the development and reuse of IP cores. It provides a standardized way to describe, manage, and build hardware projects, facilitating collaboration and reducing duplication of effort in FPGA and ASIC development. ​

hls4ml is an open-source framework that enables machine learning models to be implemented directly on hardware such as FPGAs and ASICs using high-level synthesis techniques. The system converts trained neural network models from common machine learning frameworks into hardware description code suitable for ultra-low-latency inference. This approach allows machine learning algorithms to run directly on specialized hardware, making them suitable for applications that require extremely fast...

The Red Pitaya is a commercial, affordable FPGA board with fast analog inputs and outputs. This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, PyRPL (Python RedPitaya Lockbox) implements many devices that are needed for optics experiments with the Red Pitaya.

This is a set of manually created hex programs in a Cthulhu Path to madness fashion. Which only have the goal of creating a bootstrapping path to a C compiler capable of compiling GCC, with only the explicit requirement of a single 1 KByte binary or less. Additionally, all code must be able to be understood by 70% of the population of programmers. If the code can not be understood by that volume, it needs to be altered until it satisfies the above requirement.

darc, the Durham Adaptive optics Real-time Controller. For documentation or darctalk client only, select "View all files". For the latest bleeding-edge version, please use: git clone git://git.code.sf.net/p/darc2/code darc (no password required) (this changed May 2013 due to a sourceforge update). If you use darc, please cite with: Basden, A and Myers, R, MNRAS Vol 242, page 1483, 2012

This (Python) tool allows you to easily create FPGA bitfiles for your embedded system, from several Open Source IPs (compatibles with the OpenCores Wishbone bus) . It will also generates the corresponding drivers (currently only Linux ones).

...We write this software for the development and the validation of our instrument, the Low Frequency Receiver(LFR) for the Solar Orbiter mission. This instrument is based on an actel FPGA hosting a LEON3FT processor and some peripherals. To make it more collaborative, we use a plugin based system, the main executable is SocExplorer then all the functionality are provided by plugins. Like this everybody can provide his set of plugins to handle a new SOC or just a new peripheral. SocExplorer uses PythonQt to allow user to automate some tasks such as loading some plugins, configuring them and talking with his device. ...

The OpenFire processor is a Xilinx MicroBlaze-compatible processor being modified for use in Cyber Physical Systems research. This material is based upon work supported by the National Science Foundation under Grant No. CPS-0932113.

This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks.

Development of a USB interface library to different USB enabled development (hardware) platforms. Including, but not limited to, FPGA prototype boards.

The "RISC-0" project is a collection of Python libraries and programs to support the RISC architecture described by Prof. Niklaus Wirth on his web page (http://www.inf.ethz.ch/personal/wirth/Articles/FPGA-relatedWork/index.html)