Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.

Project Samples

Finite State Machine Editor Signs Eclipse plugin running a netlist simulation

Project Activity

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Categories

Electronic Design Automation (EDA)

License

BSD License

Follow Signs - VHDL Hardware Developement

Signs - VHDL Hardware Developement Web Site

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Additional Project Details

Operating Systems

Linux, BSD, Windows

Languages

English

Intended Audience

Science/Research, Education, Developers

User Interface

Java SWT, Console/Terminal, Command-line, Eclipse

Programming Language

JavaScript, Java

Related Categories

JavaScript Electronic Design Automation (EDA) Software, Java Electronic Design Automation (EDA) Software

Registered

2002-10-10
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