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Signs - VHDL Hardware Developement

alpha

by guenter, holstsn


Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.


http://signs.sourceforge.net





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Release Date:

2007-01-11

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Registered:

2002-10-10

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