The H.264 VHDL core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream. Simple, fully synchronous design with low gate count.

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Categories

Codec, Realtime Processing

License

GNU General Public License version 2.0 (GPLv2)

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Additional Project Details

Intended Audience

Telecommunications Industry

Programming Language

VHDL/Verilog

Related Categories

VHDL/Verilog Codec Software, VHDL/Verilog Realtime Processing Software

Registered

2007-12-03
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