H.264 VHDL

planning
5.0 Stars (1)
0 Downloads (This Week)
Last Update:

Description

The H.264 VHDL core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream. Simple, fully synchronous design with low gate count.

H.264 VHDL Web Site

KEEP ME UPDATED

User Ratings

★★★★★
★★★★
★★★
★★
1
0
0
0
0
ease 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 0 / 5
features 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 0 / 5
design 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 0 / 5
support 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 0 / 5
Write a Review

User Reviews

  • vishnunj
    1 of 5 2 of 5 3 of 5 4 of 5 5 of 5

    Creative.. and useful for me

    Posted 08/17/2010
Read more reviews

Additional Project Details

Intended Audience

Telecommunications Industry

Programming Language

VHDL/Verilog

Registered

2007-12-03
Screenshots can attract more users to your project.
Features can attract more users to your project.