Menu
▾
▴
[sdcc-devel] [ sdcc-Feature Requests-1000079 ] superflous moves
|
From: SourceForge.net <no...@so...> - 2006-12-30 22:09:40
|
Feature Requests item #1000079, was opened at 2004-07-29 14:33 Message generated for change (Settings changed) made by bernhardheld You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=350599&aid=1000079&group_id=599 Please note that this message will contain a full copy of the comment thread, including the initial issue submission, for this request, not just the latest update. Category: None Group: None >Status: Closed Priority: 5 Private: No Submitted By: Nobody/Anonymous (nobody) >Assigned to: Bernhard Held (bernhardheld) Summary: superflous moves Initial Comment: I has found bug in SDCC codegenerator: Source: #include <8051.h> static unsigned int temp; unsigned int test1(unsigned int arg) { register unsigned int tmp; tmp=arg; tmp>>= 1; temp=tmp; return tmp; } unsigned int test2(unsigned int arg) { register unsigned int tmp; tmp=arg; tmp<<= 1; temp=tmp; return tmp; } void main(void) { } SDCC run command: sdcc --verbose --model-small --peep-asm -mmcs51 -- iram-size 128 --xram-size 0 --code-size 4096 -- nojtbound test.c SDCC version: SDCC : mcs51/gbz80/z80/avr/ds390/pic16/pic14/TININative/xa51 /ds400/hc08 2.4.3 #779 (Jul 28 2004) (MINGW32) Asm list: 305 ;------------------------------ ------------------------------ 306 ;Allocation info for local variables in function 'test1' 307 ;------------------------------ ------------------------------ 308 ;arg Allocated to registers r2 r3 309 ;tmp Allocated to registers r2 r3 310 ;------------------------------ ------------------------------ 311 ;test.c:5: unsigned int test1 (unsigned int arg) 312 ; --------------------------- -------------- 313 ; function test1 314 ; --------------------------- -------------- 0031 315 _test1: 0002 316 ar2 = 0x02 0003 317 ar3 = 0x03 0004 318 ar4 = 0x04 0005 319 ar5 = 0x05 0006 320 ar6 = 0x06 0007 321 ar7 = 0x07 0000 322 ar0 = 0x00 0001 323 ar1 = 0x01 324 ; genReceive 0031 AA 82 325 mov r2,dpl 326 ;test.c:9: tmp>>= 1; 327 ; genRightShift 328 ; genRightShiftLiteral 329 ; genrshTwo 330 ; Peephole 244.b moving first to a instead of r3 0033 E5 83 331 mov a,dph 0035 FB 332 mov r3,a <= Wasted mov 0036 C3 333 clr c 0037 13 334 rrc a 0038 CA 335 xch a,r2 0039 13 336 rrc a 003A CA 337 xch a,r2 003B FB 338 mov r3,a <= OK 339 ;test.c:10: temp=tmp; 340 ; genAssign 003C 8A*00 341 mov _temp,r2 003E 8B*01 342 mov (_temp + 1),r3 343 ;test.c:11: return tmp; 344 ; genRet 0040 8A 82 345 mov dpl,r2 0042 8B 83 346 mov dph,r3 0044 347 00101$: 0044 22 348 ret 349 ;------------------------------ ------------------------------ 350 ;Allocation info for local variables in function 'test2' 351 ;------------------------------ ------------------------------ 352 ;arg Allocated to registers r2 r3 353 ;tmp Allocated to registers r2 r3 354 ;------------------------------ ------------------------------ 355 ;test.c:14: unsigned int test2 (unsigned int arg) 356 ; --------------------------- -------------- 357 ; function test2 358 ; --------------------------- -------------- 0045 359 _test2: 360 ; genReceive 0045 AA 82 361 mov r2,dpl 362 ;test.c:18: tmp<<= 1; 363 ; genLeftShift 364 ; genLeftShiftLiteral 365 ; genlshTwo 366 ; Peephole 244.b moving first to a instead of r3 0047 E5 83 367 mov a,dph 0049 FB 368 mov r3,a <= Wasted mov 004A CA 369 xch a,r2 004B 25 E0 370 add a,acc 004D CA 371 xch a,r2 004E 33 372 rlc a 004F FB 373 mov r3,a <= Wated mov 374 ;test.c:19: temp=tmp; 375 ; genAssign 0050 8A*00 376 mov _temp,r2 0052 8B*01 377 mov (_temp + 1),r3 378 ;test.c:20: return tmp; 379 ; genRet 0054 8A 82 380 mov dpl,r2 0056 8B 83 381 mov dph,r3 0058 382 00101$: 0058 22 383 ret Bug appears under any literal shift (left or right, char or int). for event of shift on 1 bit (left or right, char or int) i has corrected this by the next peephole rules: replace { mov r%1,a add a,acc mov r%1,a } by { ; Peephole R.5 optimized char left shift literal 1 add a,acc mov r%1,a } replace { mov r%1,a clr c rrc a mov r%1,a } by { ; Peephole R.5 optimized char right shift literal 1 clr c rrc a mov r%1,a } replace { mov r%1,a xch a,r%2 add a,acc xch a,r%2 rlc a mov r%1,a } by { ; Peephole R.5 optimized int left shift literal 1 xch a,r%2 add a,acc xch a,r%2 rlc a mov r%1,a } replace { mov r%1,a clr c rrc a xch a,r%2 rrc a xch a,r%2 mov r%1,a } by { ; Peephole R.5 optimized int right shift literal 1 clr c rrc a xch a,r%2 rrc a xch a,r%2 mov r%1,a } BUT, this is the codegenerator bug! It needs for correction. With the best wishes, Ruslan. ---------------------------------------------------------------------- >Comment By: Bernhard Held (bernhardheld) Date: 2006-12-30 23:09 Message: Logged In: YES user_id=203539 Originator: NO Symptom removed in SDCC rev. 4540 ---------------------------------------------------------------------- Comment By: Bernhard Held (bernhardheld) Date: 2004-07-29 16:31 Message: Logged In: YES user_id=203539 You'll find superflous moves all over SDCC's assembly code, not only around shifts. This is a well known phenomenon, which has been reported more than once. As long as the generated code is correct, this isn't really a bug. ---------------------------------------------------------------------- You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=350599&aid=1000079&group_id=599 |