[sdcc-devel] Need Help With DS80C320

[Moises E. <esc...@ya...>]

/*
 *
 * sdcc_reg320.h
 *
 * Author: Moises Escobedo
 *
 *
 * Special Function Register definitions file
 * DS80C320/23
 *
 *
 */
 
#ifndef	__REG320_H__
#define	__REG320_H__

/* BYTE Registers */
sfr at  0x80 P0;
sfr at	0x81 SP;
sfr at	0x82 DPL;
sfr at	0x83 DPH;
sfr at	0x84 DPL1;
sfr at  0x85 DPH1;
sfr at  0x86 DPS;
sfr at	0x87 PCON;
sfr at  0x88 TCON;
sfr at	0x89 TMOD;
sfr at  0x8A TL0;
sfr at  0x8B TL1;
sfr at  0x8C TH0;
sfr at  0x8D TH1;
sfr at  0x8E CKCON;
sfr at  0x90 P1;
sfr at  0x91 EXIF;
sfr at  0x98 SCON0;
sfr at  0x99 SBUF0;
sfr at  0xA0 P2;
sfr at  0xA8 IE;
sfr at  0xA9 SADDR0;
sfr at  0xAA SADDR1;
sfr at  0xB0 P3;
sfr at  0xB8 IP;
sfr at  0xB9 SADEN0;
sfr at  0xBA SADEN1;
sfr at  0xC0 SCON1;
sfr at  0xC1 SBUF1;
sfr at  0xC5 STATUS;
sfr at  0xC7 TA;
sfr at  0xC8 T2CON;
sfr at  0xC9 T2MOD;
sfr at  0xCA RCAP2L;
sfr at  0xCB RCAP2H;
sfr at  0xCC TL2;
sfr at  0xCD TH2;
sfr at  0xD0 PSW;
sfr at  0xD8 WDCON;
sfr at  0xE0 ACC;
sfr at  0xE8 EIE;
sfr at  0xF0 B;
sfr at  0xF8 EIP;

/* BIT Registers */

/* Port PO */
sbit at 0x80 P0_0;
sbit at 0x81 P0_1;
sbit at 0x82 P0_2;
sbit at 0x83 P0_3;
sbit at 0x84 P0_4;
sbit at 0x85 P0_5;
sbit at 0x86 P0_6;
sbit at 0x87 P0_7;

/* TCON at 0x88 */
sbit at 0x88 IT0;
sbit at 0x89 IE0;
sbit at 0x8A IT1;
sbit at 0x8B IE1;
sbit at 0x8C TR0;
sbit at 0x8D TF0;
sbit at 0x8E TR1;
sbit at 0x8F TF1;

/* Port P1 */
sbit at 0x90 P1_0;
sbit at 0x91 P1_1;
sbit at 0x92 P1_2;
sbit at 0x93 P1_3;
sbit at 0x94 P1_4;
sbit at 0x95 P1_5;
sbit at 0x96 P1_6;
sbit at 0x97 P1_7;

/* SCON0 */
sbit at 0x98 RI_0;
sbit at 0x99 TI_0;
sbit at 0x9A RB8_0;
sbit at 0x9B TB8_0;
sbit at 0x9C REN_0;
sbit at 0x9D SM2_0;
sbit at 0x9E SM1_0;
sbit at 0x9F SM0_0;
sbit at 0x9F FE_0;

/* Port P2 */
sbit at 0xA0 P2_0;
sbit at 0xA1 P2_1;
sbit at 0xA2 P2_2;
sbit at 0xA3 P2_3;
sbit at 0xA4 P2_4;
sbit at 0xA5 P2_5;
sbit at 0xA6 P2_6;
sbit at 0xA7 P2_7;

/* IE at 0xA8 */
sbit at 0xA8 EX0;
sbit at 0xA9 ET0;
sbit at 0xAA EX1;
sbit at 0xAB ET1;
sbit at 0xAC ES0;
sbit at 0xAD ET2;
sbit at 0xAE ES1;
sbit at 0xAF EA;

/* Port P3 */
sbit at 0xB0 P3_0;
sbit at 0xB1 P3_1;
sbit at 0xB2 P3_2;
sbit at 0xB3 P3_3;
sbit at 0xB4 P3_4;
sbit at 0xB5 P3_5;
sbit at 0xB6 P3_6;
sbit at 0xB7 P3_7;

/* IP AT 0xB8 */
sbit at 0xB8 PX0;
sbit at 0xB9 PT;
sbit at 0xBA PX1;
sbit at 0xBB PT1;
sbit at 0xBC PS0;
sbit at 0xBD PT2;
sbit at 0xBE PS1;

/* SCON AT 0xC0 */
sbit at 0xC0 RI_1;
sbit at 0xC1 TI_1;
sbit at 0xC2 RB8_1;
sbit at 0xC3 TB8_1;
sbit at 0xC4 REN_1;
sbit at 0xC5 SM2_1;
sbit at 0xC6 SM1_1;
sbit at 0xC7 SM0_1;

/* T2CON at 0xC8 */
sbit at 0xC8 CP_RL_2;
sbit at 0xC9 C_T_2;
sbit at 0xCA TR_2;
sbit at 0xCB EXEN_2;
sbit at 0xCC TCLK;
sbit at 0xCD RCLK;
sbit at 0xCE EXF_2;
sbit at 0xCF TF_2;

/* PSW at 0xD0 */
sbit at 0xD0 PARITY;
sbit at 0xD0 P;
sbit at 0xD1 F1;
sbit at 0xD2 OV;
sbit at 0xD3 RS0;
sbit at 0xD4 RS1;
sbit at 0xD5 F0;
sbit at 0xD6 AC;
sbit at 0xD7 CY;

/* WDCON at 0xD8 */
sbit at 0xD8 RWT;
sbit at 0xD9 EWT;
sbit at 0xDA WTRF;
sbit at 0xDB WDIF;
sbit at 0xDC PFI;
sbit at 0xDD EPFI;
sbit at 0xDE POR;
sbit at 0xDF SMOD_1;

/* EIE at 0xE8 */
sbit at 0xE8 EX2;
sbit at 0xE9 EX3;
sbit at 0xEA EX4;
sbit at 0xEB EX5;
sbit at 0xEC EWDI;

/* EIP at 0xF8 */
sbit at 0xF8 PX2;
sbit at 0xF9 PX3;
sbit at 0xFA PX4;
sbit at 0xFB PX5;
sbit at 0xFC PWDI;

/* Interrupt Vectors */
#define PFI_INT		0x33		/* Power Fail Interrupt */
#define INT0_INT	0x03		/* External Interrupt 0 */
#define TF0_INT		0x0B		/* Timer 0 Interrupt */
#define INT1_INT 	0x13		/* External Interrupt 1 */
#define TF1_INT		0x1B		/* Timer 1 Interrupt */
#define SCON0_INT	0x23		/* Serial Port 0 Interrupt */
#define TF2_INT		0x2B		/* Timer 2 Interrupt */
#define SCON1_INT	0x3B		/* Serial Port 1 Interrupt */
#define INT2_INT	0x43		/* External Interrupt 2 */
#define INT3_INT 	0x4B		/* External Interrupt 3 */
#define INT4_INT	0x53		/* External Interrupt 4 */
#define INT5_INT	0x5B	    /* External Interrupt 5 */
#define WDTI_INT	0x63		/* Watchdog Timeout Interrupt */


#endif