From: Todd Greenwood-G. <t.g...@gm...> - 2013-02-17 21:57:59
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I'm new to EE, and trying to learn analog, digital, + vhdl. I don't have any hardware, so I'm trying this all via open source digital toolkits. I thought I'd try to create simple VHDL components, and then use QUCS to test them, in circuit. I'm using myHDL to generate the VHDL (http://www.myhdl.org/doku.php). My issue seems to be that QUCS cannot seem to process an include file because it doesn't know what to do with the 'work' namespace... Short Example: File # 1: Inc.vhd ----------------- -- import line chokes on 'work' in QUCS/freeHDL -- File: Inc.vhd -- Generated by MyHDL 0.7 -- Date: Sun Feb 17 10:37:41 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_07.all; ... <snip> File # 2: pck_myhdl ------------------- -- File: pck_myhdl_07.vhd -- Generated by MyHDL 0.7 -- Date: Sun Feb 17 10:37:41 2013 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package pck_myhdl_07 is attribute enum_encoding: string; ... <snip> Error ----- >>> work.pck_myhdl_07 is undeclared I've tried various things to work around this...copying the include file into the target vhdl, copying the include file next to the source vhdl file, etc. Questions: 1. Can someone point me at some examples using VHDL and QUCS? free 2. How can I look at the exact commands QUCS is using to process the VHDL (presumably it's calling into freeHDL...) 3. If I have to manually copy the included file, 'work.pck_myhdl_07', in this case, ...what does that need to look like? 4. Is QUCS the appropriate tool to use for this sort of thing (i.e. learning about electronics, vhdl, circuits, etc?) Project attached as tgz. -Todd |