#37 synthesis support


Are there any future plans to re-introduce synthesis support into Icarus?
Assuming there are no such plans are there any other open source synthesis alternatives you can recommend?
Thank you for your great work on Icarus.


  • orens

    Sorry I forgot to add this earlier to the bug report.
    Below is more information about the issue:
    The fpga target for synthesis does not seem to be included in the latest windows or linux build.
    The files fpga.conf and fpga.tgt are missing.
    The error message is:
    ERROR: Unable to read config file: C:\iverilog\lib\ivl\fpga.conf
    error: failed to load.
    : The specified module could not be found.
    When I try to manually compile the fpga target there are compilation errors in xilinx.c .

  • Cary R.
    Cary R.

    V0.8 was the last release to include working support for synthesis. There were significant changes in the compiler when developing V0.9 and these changes broke the synthesis code. We would like to eventually add support back in for synthesis, but the priority has been enhancing/fixing the Verilog support first. Steve has the whole story, but as I understand it, the rational for dropping support for synthesis was that the existing vendor supplied FPGA synthesis tools had become as good or better than what Icarus had so he decided that keeping synthesis support was a low priority.

    Using V0.8 for synthesis is an acceptable work flow, but you need to be able to live with the limitations it has. It can be installed and the latest release should automatically build with a suffix so you can keep the current release for simulation and use V0.8 for synthesis.

    I'm currently working on a Verilog to Verilog-95 converter in development that once complete could be used to automatically convert more advanced Verilog code into something that V0.8 would understand. There are numerous limitation with this and since the code isn't finished I don't know exactly what will and won't be correctly converted.

    So in summary V0.8 was the last release to have working synthesis. We would like to add synthesis support back into a later release, but there is no formal schedule for when this will happen. Steve may change this to a feature request or drop the priority of this report since it is outside our current plans.

    FYI someone posted about a new open source synthesis tool on the comp.lang.verilog newsgroup. Please let us know if V0.8 or this other tool satisfies your needs.

  • orens

    Thank you, Cary.
    I tested version V0.8 and it seems to work fine.
    I also tried the new Synthesis project(HANA?) It looks interesting but it doesn’t seem to generate Synthesis output on the test cases I tried.
    I will update if I have something new.

  • Cary R.
    Cary R.

    I'll also add that I fixed a few synthesis bugs/limitations a month or so ago. There is also preliminary support for latch synthesis. All this is in the latest V0.8 code from git. Ideally we would finish the latch synthesis (make it more robust, etc.) and then create a new release. Given that we are mostly focused on other things this may never happen so getting the latest from git may be the best choice.

  • I'll weigh in on this too. Synthesis support is pretty low priority. Higher priorities are improved SystemVerilog support, some minimal VHDL (mixed language) support, and Verilog-A/MS support. At least those are my personal priorities.

    I have been getting a lot of synthesis support questions lately. A high percentage of those are from people who do not really understand the distinction between simulating a design intended for a specific target and actually synthesizing for that target. Icarus Verilog is very good at the former. The technology vendors are good at (and usually supply free tools for) synthesizing for their own technologies. So there really is little motivation to actually do synthesis in Icarus Verilog.

    So I'm going to shift this report over to "Feature Requests".

    • milestone: 530321 -->
    • labels: 1138880 -->
  • orens

    Hi Steve,
    Thank you for weighing in on this.
    What about extending support for EDIF LPM format?
    LPM is hardware agnostic yet can be optimized for specific hardware synthesis by third party tools.
    Assuming it is not possible somehow to set the IVerilog target output to EDIF LPM in the current code branch (please correct me if I’m wrong!).
    I am considering adding LPM level synthesis support to the current version of Icarus Verilog.
    Do you have any recommendations or reservations against taking this path?
    Thank you in advance