#35 Xilinx secureIP support?

[Kevin Smith]

I was doing great with Icarus on a Xilinx design until I ran into a hardware-vendor-provided, coregen-generated IP core of the DDR2 memory controller block.

This contains an encrypted hunk of code so I had to switch to ISIM (which is doing horrible things to me). What is required to support this kind of file? Is it impossible because of licensing issues?
--
Keb'm

[Stephen Williams]

This question (specifically WRT Xilinx protected IP) comes up once in a while. I too would love a means to simulate Xilinx's coregen IP cores, but alas they are encrypted.

My understanding is that they use the `protect feature of Verilog (when generating Verilog) and that is defined as part of the IEEE1364-2005 standard. I had looked into implementing it, but it didn't take me to long to realize the obvious: if Icarus Verilog can simulate encrypted Verilog, it can just as easily be used to decrypt the protected core.

I would love to get together with Xilinx and work out a solution that would allow Icarus Verilog users to be able to simulate Xilinx cores, but I haven't been able to hold their interest in this.

[Cary R.]

I personally do not see how this functionality could be implemented in an open source simulator. Yes we could likely devise a method to create and keep a secret key, but like Steve said once the run time had read the secret key and started reading the encrypted information someone could modify the code to dump the information instead of simulating with it. Unless someone has an idea on how this could be done that can't be attacked I think this request needs to be closed. If we can't think of a way to do this we should add something to the wiki stating why this isn't possible.