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#993 Synthesis does not support some common styles for coding flip-flops

devel
closed-fixed
nobody
None
4
2016-02-21
2015-08-20
No
$ iverilog -V | grep "version 1"
Icarus Verilog version 11.0 (devel) (s20150603-96-g19009ec)
Icarus Verilog Preprocessor version 11.0 (devel) (s20150603-96-g19009ec)
Icarus Verilog Parser/Elaborator version 11.0 (devel) (s20150603-96-g19009ec)
$ iverilog -Wall mp_proc.v
$ iverilog -Wall mp_proc.v -t sizer
mp_proc.v:8: warning: Process not synthesized.
mp_proc.v:8: warning: Process not synthesized.
mp_proc.v:8: warning: Process not synthesized.
ivl: t-dll.cc:1062: virtual void dll_target::logic(const NetLogic*): Assertion `nex->t_cookie()' failed.
Aborted

This example stripped down from working, tested production code.

1 Attachments

Related

Bugs: #993

Discussion

  • Martin Whitaker

    Martin Whitaker - 2016-01-30
    • summary: assertion in synth --> Synthesis does not support some common styles for coding flip-flops
     
  • Martin Whitaker

    Martin Whitaker - 2016-01-30

    I've pushed a temporary fix for this to both the master and v10 branches, that outputs a "sorry" message instead of an assertion failure. Currently synthesis does not support the styles of coding flip-flops that use multiple statements, e.g.

    q <= 0;
    if (a) q <= d;
    

    or

    if (clr) q <= 0;
    if (set) q <= 1;
    

    I don't think it would be too hard to support this - but I'm out of time tonight. I'll change the bug title to reflect where we are now.

     
  • Martin Whitaker

    Martin Whitaker - 2016-02-21
    • status: open --> closed-fixed
     
    • Stephen Williams

      This will probably be a bit much for a stable branch, so I'd
      say to not worry about porting into the v10 branch.

      On 02/21/2016 03:41 PM, Martin Whitaker wrote:

      • status: open --> closed-fixed
      • Comment:

      Well, it turned out to be quite a bit harder than I thought, but this is
      now fixed in the master branch. This could be back-ported to v10, but
      I'll leave it to mature a bit first.


      [bugs:#993] http://sourceforge.net/p/iverilog/bugs/993/ Synthesis
      does not support some common styles for coding flip-flops

      Status: closed-fixed
      Group: devel
      Created: Thu Aug 20, 2015 08:35 PM UTC by Larry Doolittle
      Last Updated: Sat Jan 30, 2016 10:54 PM UTC
      Owner: nobody
      Attachments:

      $ iverilog -V | grep "version 1"
      Icarus Verilog version 11.0 (devel) (s20150603-96-g19009ec)
      Icarus Verilog Preprocessor version 11.0 (devel) (s20150603-96-g19009ec)
      Icarus Verilog Parser/Elaborator version 11.0 (devel) (s20150603-96-g19009ec)
      $ iverilog -Wall mp_proc.v
      $ iverilog -Wall mp_proc.v -t sizer
      mp_proc.v:8: warning: Process not synthesized.
      mp_proc.v:8: warning: Process not synthesized.
      mp_proc.v:8: warning: Process not synthesized.
      ivl: t-dll.cc:1062: virtual void dll_target::logic(const NetLogic*): Assertion `nex->t_cookie()' failed.
      Aborted

      This example stripped down from working, tested production code.


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      --
      Steve Williams "The woods are lovely, dark and deep.
      steve at icarus.com But I have promises to keep,
      http://www.icarus.com and lines to code before I sleep,
      http://www.picturel.com And lines to code before I sleep."

       

      Related

      Bugs: #993

  • Martin Whitaker

    Martin Whitaker - 2016-02-21

    Well, it turned out to be quite a bit harder than I thought, but this is now fixed in the master branch. This could be back-ported to v10, but I'll leave it to mature a bit first.

     

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