#740 Timing checks are not supported.

[Anonymous]

Using $setuphold with negative timing check options that were introduced in Verilog2001 does not appear do operate correctly with Iverilog v0.9.1

Sample code and simulation script attached.

Nets dly_CK and dly_D are not generated by the $setuphold command (left unknown at 1'bZ) in DFF1 module, therefore n0 is also left untouched and the output Q of the cell is not updated properly.
Module DFF0 does not use the negative timing check options are, and does not show the problem.

[Nobody/Anonymous]

Testbench and sample code

[Cary R.]

Icarus does not support any timing checks. By default the entire specify block is ignored and must be enabled with -gspecify. Most of the delays work as expected, but there are conditional cases that have problems. Some time next year I plan to add a different way to handle expressions. This should fix the conditional delays and will also be needed to add timing checks. This fix will not ever be available in the V0.9 branch. I am switching the group to development and renaming the report to reflect the true issue. We expect this to be in the V0.10 release whenever that happens.

Because of all the foundational work that needs to be done first this will not be fixed quickly.

[Cary R.]

I looked at this very briefly and since we do not have working timing checks the delayed signals are not driven as you noted. If these were driven appropriately your simulation may work except for the timing checks. We may be able to fix this part of the problem before adding the full timing checks, but because of our schedules even this will likely not happen quickly. Both $setuphold and $recrem need to support delayed signals.

I have submitted a patch that prints a warning message that the delayed signals will not be driven when the circuit is compiled.