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#560 Integer Division Remainder Bug

v0.8
closed-wont-fix
nobody
5
2008-11-14
2008-11-07
No

Hi,

Details of the bug follows:

<code>

module bug05_integerRem;

reg signed[31:0] reg0;
reg signed[31:0] reg1;
wire signed[31:0] dividend=reg0;
wire signed[31:0] divisor=reg1;
wire signed[31:0] remainder;

assign remainder= dividend%divisor;

initial begin
reg0=32'hffffffff;
reg1=32'h0d1f0796;
//BUG here: remainder==32'h06b26fdd, should be 32'hffffffff
#100 $display("dividend=%h divisor=%h remainder=%h expected output=ffffffff",dividend,divisor,remainder);
$display("reg0=%h reg1=%h reg0%%reg1=%h expected output=ffffffff",reg0,reg1,reg0%reg1);
end

endmodule

</code>

I think it is normal for this not to give the expected result in synthesis but it should do well in icarus verilog.

I am using version 0.8.6.

Best regards,

Sadi.

Discussion

  • Cary R.
    Cary R.
    2008-11-07

    See the integer division report for more info.

     
  • Cary R.
    Cary R.
    2008-11-07

    • priority: 5 --> 6
    • assigned_to: nobody --> caryr
    • milestone: 530319 --> 530321
     
  • Cary R.
    Cary R.
    2008-11-08

    I have submitted a patch for the development branch that fixes this and more. I'm returning the report to V0.8.

     
  • Cary R.
    Cary R.
    2008-11-08

    • priority: 6 --> 5
    • milestone: 530321 --> v0.8
    • assigned_to: caryr --> nobody
     
  • Cary R.
    Cary R.
    2008-11-14

    V0.8 has very limited support for signed and adding this is a major undertaking so we have decided that we will not fix this in V0.8. Use 0.9.devel if you need this functionality.

     
  • Cary R.
    Cary R.
    2008-11-14

    • status: open --> closed-wont-fix