#53 Synthesis fails for user defined functions

v0.8
open
nobody
Other (110)
4
2009-01-27
2006-06-15
No

The example below comes from Synopsys Design Compiler
documentation, and synthesizes just fine with DC - into
108 and/or/inv gates. Icarus produces the cryptic error
message "unknown LPM type 14" - now I found (in the
source code :-) that "type 14" means "user defined
function", but this does not help a lot.

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv

15:37:34 [feliks@mars ~/MyProjects/SynopsysDC/tut/cnt-
combin]$iverilog -v
Icarus Verilog version 0.8.2 ($Name: v0_8_2 $)
Copyright 1998-2003 Stephen Williams
This program is free software; you can redistribute it
and/or modify
it under the terms of the GNU General Public License as
published by
the Free Software Foundation; either version 2 of the
License, or
(at your option) any later version.

This program is distributed in the hope that it will be
useful,
but WITHOUT ANY WARRANTY; without even the implied
warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the
GNU General Public License for more details.

You should have received a copy of the GNU General
Public License
along with this program; if not, write to the Free
Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston,
MA 02111-1307, USA

iverilog: No input files.
Usage: iverilog [-ESvV] [-B base] [-c cmdfile] [-g1|-g2|-
g3.0]
[-D macro[=defn]] [-I includedir] [-M
depfile] [-m module]
[-N file] [-o filename] [-p flag=value]
[-s topmodule] [-t target] [-T min|typ|
max]
[-W class] [-y dir] [-Y suf]
source_file(s)
See man page for details.
15:52:51 [feliks@mars ~/MyProjects/SynopsysDC/tut/cnt-
combin]$iverilog cnt-combin.v
15:53:06 [feliks@mars ~/MyProjects/SynopsysDC/tut/cnt-
combin]$iverilog -S -t edif -o edif.out cnt-combin.v
fpga.tgt: unknown LPM type 14
fpga.tgt: unknown LPM type 14
15:53:23 [feliks@mars ~/MyProjects/SynopsysDC/tut/cnt-
combin]$cat cnt-combin.v
module count_zeros(in, out, error);
input [7:0] in;
output [3:0] out;
output error;

function legal;
input [7:0] x;
reg seenZero, seenTrailing;
integer i;

begin : _legal_block
legal = 1; seenZero = 0; seenTrailing = 0;
for ( i=0; i <= 7; i=i+1 )
if ( seenTrailing && (x[i] == 0) ) begin
legal = 0;
disable _legal_block;
end
else if ( seenZero && (x[i] == 1) )
seenTrailing = 1;
else if ( x[i] == 0 )
seenZero = 1;
end
endfunction

function [3:0] zeros;
input [7:0] x;
reg [3:0] count;
integer i;

begin
count = 0;
for ( i=0; i <= 7; i=i+1 )
if ( x[i] == 0 ) count = count + 1;
zeros = count;
end
endfunction

wire is_legal = legal(in);
assign error = ! is_legal;
assign out = is_legal ? zeros(in) : 0;
endmodule

Discussion

  • Logged In: YES
    user_id=97566

    Icarus Verilog does not know how to synthesize user defined functions.
    I will leave this bug report open, but I will lower the priority one step to
    reflect this is really beyond the skills for the synthesizer.

    For the record, this code should simulate just fine.

     
    • priority: 5 --> 4
     
  • Cary R.
    Cary R.
    2009-01-27

    • summary: Synthesis fails for simple example --> Synthesis fails for user defined functions