Justin Fisher

Before the days of Verilog-A, I used to get by with spice macros, and they worked just as well. That said, I've spent the last 2 or 3 months trying to get Verilog-A fully functional and playing nice with NGSPICE. Its taken far longer than I thought it would, but it's almost at a testable level. I'll release it soonish. Within the next 2 or 3 weeks. -- Kind regards, Justin Fisher.

Added device array capability. Eg R1<1:0>

added some new devices parameters for FinFET processes

Even without the prior state the hysterisis can't show you, the trip point in a DC sweep is going to be somewhere near the 2 trip points. You'll never see it in transient though, because 500us is far to fast. Your quite sure though, so please go ahead, flail around, and ask design related questions instead of simply running a sensible simulation. -- Kind regards, Justin Fisher. On Mon, Mar 2, 2026, 11:48 Holger Vogt h_vogt@users.sourceforge.net wrote: A circuit with hysteresis has an input range...

Without having an opportunity to look at what you're doing... what is the speed of your input in transient? If it's anything other than very slow indeed, you won't get a good idea of the threshold voltages. -- Kind regards, Justin Fisher.

Are you using Cadence to netlist? Why not just run the netlister to output an HSPICE netlist? Cadence can do that. -- Kind regards, Justin Fisher.

The models I used were characterized to -40C and worked just fine down to -40C There's no reason they shouldn't. -- Kind regards, Justin Fisher.

You have specified VSIG twice. You have a whole load of constants that aren't defined. What is the value of 13.0TP? -- Kind regards, Justin Fisher.