Verilog syntax highlight

Have you some more details about Verilog? Comment chars? Keywords? And what is the file pattern from Verilog files?

Greetings,
Tim

Hi Tim,

Here are the Verilog syntax details:
Line comment: // <-- anything after '//' is commented till the end of the line
Block comment start: /*
Block comment end: */
List of Verilog keywords: http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/verilog10.html

This link shows the examples of comments in verilog: http://www.asic-world.com/verilog/syntax1.html

Compiler Directives: `define, `include, `ifdef, `ifndef, `else, `endif http://www.asic-world.com/verilog/compiler1.html

A 'verilog line' always ends with a semicolon ';'
A 'verilog line' can have newline characters in between... the verilog compiler keeps reading the line as one whole line till the point it sees a semicolon.
example:
assign a =
b +
c + d - e;

is same as

assign a = b+c+d-e;

This was a very crude primer to Verilog syntax.

I use Notepad++... it's got very good Verilog syntax highlighting... could that help you retrieve more info on Verilog syntax?

I also googled a Perl module that does Verilog syntax highlighting.. perhaps that will give you a more structured info:
http://search.cpan.org/src/HANJE/Syntax-Highlight-Engine-Kate-0.04/lib/Syntax/Highlight/Engine/Kate/Verilog.pm

I hope this helps.

Thanks!!

Kaushal

Yes, I think this informations will help. Thanks!

Can you assigned the RFE to me? As reminder! ;)

I think I understood what you meant by RFE, but don't known the exact full form :)
Request For ** ?

Thanks for taking this request!

RFE = Request Feature Enhancement

Sorry, RFE is the old name from this "Feature Requests" tracker. SF.net change it once, but it seems , I use it still. ;-)

I have no rights to change the "Assigned" field from "Nobody/Anonymous" to "gerundt". You, which create this feature request, or a project admin can do it.

original and altered files

Ok, upload the Verilog syntax highlighter code to this item. I used the C++ highlighter as start and use keyword-lists from SciTE <http://www.scintilla.org/>. (Its the base from Notepad++ too).

Sorry I missed discussion in this item (feature request have been very low in my priorities).

I quickly looked at the patch. Looks good (if it compiles, didn't try that :).

Can you add some example verilog file to /Testing/Fileformats (or some such folder name) so we don't need to hunt files from net later on...

Committed to SVN (In Revision 6093; Trunk)...

> Can you add some example verilog file to /Testing/Fileformats (or some
> such folder name) so we don't need to hunt files from net later on...

No problem, I had some test files for me and will make a test file for the Testing folder.

Kimmo, is this patch Trunk-only or should I commit it to branch R2_10 too (after a experimental version)?

Problem is maybe, that I added one line to Merge.rc...

This really isn't a bug fix so not for branch. And we absolutely don't want to break PO file compatibility in branch.

You forgot to update VS2003.net project file (which is our main project file now). I fixed it as a rev. 6094.

Ok, I added a Verilog test file to the "Testing\Fileformats" folder:

Committed to SVN (In Revision 6133)

Kaushal, I you want to the test the Verilog syntax highlight, you can test WinMerge 2.11.1.7:
http://sourceforge.net/project/showfiles.php?group_id=13216&package_id=92246&release_id=641776

Hi Tim and the people who worked on this,

Thanks a bunch... the Verilog files now look so much better :)

I apologize for the delay in responding... was away on Thanksgiving break. I hope you guys too had a fun-filled long weekend.

The update looks great.. can't spot any bugs right now...

Thanks once again.. will be using this update till the next stable release.

Kaushal