VHCG Files

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Name	Modified	Size	InfoDownloads / Week
Parent folder
poly_91_121_tbdepth_64_VERILOG_VHDL_RTL_TESTBENCH.zip	2010-01-29	42.6 kB	0
rag_91_121_TB120_RAMSIZE512x32.rar	2009-04-07	24.7 kB	0
Verilog_TD-SCDMA_rate_1-2_Viterbi_decoder.rar	2009-02-09	126.1 kB	0
k_9_rate_1-2_VHDL.rar	2009-01-13	24.6 kB	0
Totals: 4 Items		218.1 kB	0

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