SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

Project Activity

See All Activity >

Categories

Text Processing, Hardware, Electronic Design Automation (EDA)

License

GNU Library or Lesser General Public License version 3.0 (LGPLv3)

Follow SmGen

SmGen Web Site

Other Useful Business Software
Enterprise-grade ITSM, for every business Icon
Enterprise-grade ITSM, for every business

Give your IT, operations, and business teams the ability to deliver exceptional services—without the complexity.

Freshservice is an intuitive, AI-powered platform that helps IT, operations, and business teams deliver exceptional service without the usual complexity. Automate repetitive tasks, resolve issues faster, and provide seamless support across the organization. From managing incidents and assets to driving smarter decisions, Freshservice makes it easy to stay efficient and scale with confidence.
Try it Free
Rate This Project
Login To Rate This Project

User Reviews

Be the first to post a review of SmGen!

Additional Project Details

Operating Systems

Cygwin, MinGW/MSYS2, Linux, BSD

Intended Audience

Science/Research, Developers, Engineering

User Interface

Command-line

Programming Language

Perl, VHDL/Verilog

Related Categories

Perl Text Processing Software, Perl Hardware Platform, Perl Electronic Design Automation (EDA) Software, VHDL/Verilog Text Processing Software, VHDL/Verilog Hardware Platform, VHDL/Verilog Electronic Design Automation (EDA) Software

Registered

2010-06-11
Report inappropriate content