Verilog processor for Notepad++. Current features:

- Instantiate a module
- Insert registers/wires from a module
- Generate a test bench template
- Automatically inserts a default header for a test bench
- Insert a clocked always block

v1.2.0 now supports ANSI and non-ANSI module declarations.

To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C. This selects the module and parses its components. After this, all other functions are available.

Project Activity

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Categories

Text Editors, Integrated Development Environments (IDE), Scientific/Engineering

License

GNU General Public License version 3.0 (GPLv3)

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Additional Project Details

Intended Audience

Engineering

Programming Language

VHDL/Verilog

Related Categories

VHDL/Verilog Text Editors, VHDL/Verilog Integrated Development Environments (IDE), VHDL/Verilog Scientific Engineering

Registered

2014-07-18
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