gen_regs Files

#==============================================================================
# README
#==============================================================================

#--------------------------------------
# r2.1.0
#--------------------------------------

Updates from r2.0.1:
- Corrected write mask value computation;
- Updated check mask value computation (initial value is now the maximum value);
- Added the registers number global parameter in defined/package file;
- Updated parameters in local parameters (SystemVerilog only);
- Added register and output creation when update option is set on a field;
- Added WC, WC and WO1 field types;
- Corrected assignation width declaration in register process on read/write set/clear fields;
- Updated documentation.


#--------------------------------------
# r2.0.1
#--------------------------------------

Updates from r2.0.0:
- Corrected asynchronous read data assignation (Verilog and SystemVerilog only);
- Corrected read process in order to take into account the read enable signal;
- Removed output creation on RC and RS field types.


#--------------------------------------
# r2.0.0
#--------------------------------------

Updates from r1.1.1:
- Added field types;
- Added VHDL;
- Added options for more flexibility;
- Added SystemVerilog testbench.


#--------------------------------------
# r1.1.1
#--------------------------------------

Updates from r1.1:
- Added release information in output header files;
- Updated parameters and signals naming, corrected default read data width
  (SystemVerilog only), and corrected clock enable generation.


#--------------------------------------
# r1.1
#--------------------------------------

Updates from r1.0:
- Corrected clock enable clock generation.