User Activity

  • Committed [c18fd8]

    Added release information in output header file

  • Committed [67f032]

    Updated parameters and signals naming, correcte...

  • Committed [3489df]

    Corrected clock enable signal generation

  • Modified a wiki page on gen_regs

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  • Committed [2efb17]

    Added RWU, RW0 and RW1 support in testbench

  • Committed [724367]

    Added RWU, RW0 and RW1 field types and correcte...

  • Committed [8cbd18]

    Updated document

  • Committed [e47a6f]

    Added fields width definition

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Personal Data

Username:
vincentb38
Joined:
2016-05-16 15:34:48
Location:
France / CEST
Gender:
Male

Projects

This is a list of open source software projects that Vincent Bonnet is associated with:

  • gen_regs Registers bank RTL code generation Last Updated:

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