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cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core

As of 2015-03-14, this project may now be found at

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The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic registers.

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  • Processor model runs C code, compiled with GCC
  • Testbench includes processor, RAM, ROM and file I/O
  • Core has all forwarding paths and is fully interlocked for data and control hazards
  • Coprocessor0 is partially implemented, six hardware interrupts + NMI implemented in "Interrupt Compatibility Mode"
  • The instructions break, syscall, trap, mfc0, mtc0, eret, ei, di, ll, sc are implemented
  • Partial-word loads and stores (word, half-word, byte) implemented at the processor's memory interface


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Additional Project Details

Intended Audience

Education, Engineering

User Interface


Programming Language

Assembly, VHDL/Verilog



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