[WinAVR-users] [ winavr-Bugs-1623161 ] asm("rol r16") compiled as ("adc r16, r16")

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Bugs item #1623161, was opened at 2006-12-27 13:36
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Category: Interface (example)
Group: None
Status: Open
Resolution: None
Priority: 5
Private: No
Submitted By: Nobody/Anonymous (nobody)
Assigned to: Nobody/Anonymous (nobody)
Summary: asm("rol r16") compiled as ("adc r16,r16")

Initial Comment:
asm volatile (	/* Int1 has higher priority then Timer1, r16 is not updated */
		/* Check received bit length */
	"rcall	RC5_Test			\n\t"
	"subi	r16,12				\n\t"	/* Bit length is to short, noise received */
	"brcs	RC5_Error%=			\n\t"	"subi	r16,23			        \n\t"
	/* Bit has short lenght */			"brcs	RC5_ShortBit%=			\n\t"
	"subi	r16,23				\n\t"
	"brcs	RC5_LongBit%=			\n\t"
	/* Check if we have 14 bits received */
	"andi	r17,0x0f			\n\t"
	/* Less or more then 14 bits received try again. */
	"brne	RC5_Error%=			\n\t"
	"lds	r16,RC5_Word			\n\t"
	"mov	__tmp_reg__,r16			\n\t"
	"andi	r16,0x3f			\n\t"
	"sts	RC5_Command,r16		        \n\t"
	"mov	r16,__tmp_reg__			\n\t"
	"rol	r16				\n\t"
	"rol	r16				\n\t"
	"rol	r16				\n\t"
	"andi	r16,0x03			\n\t"
	"sts	RC5_System,r16			\n\t"
	"lds	r16,RC5_Word+1			\n\t"
	"andi	r16,0x1f			\n\t"
	"lsl	r16				\n\t"
	"lsl	r16				\n\t"
	"lds	__tmp_reg__,RC5_Command		\n\t"
	"or		__tmp_reg__,r16		\n\t"
	"sts	RC5_Command,__tmp_reg__		\n\t"
	/* Set bit 4, RC5_Valid */
	"ori	r17,0x10			\n\t"
	"rjmp	RC5_End%=			\n\t"

Compiles to=>


asm volatile (		/* Int1 has higher priority then Timer1, r16 is not updated */
 124:	56 d0       	rcall	.+172    	; 0x1d2 <RC5_Test>
 126:	0c 50       	subi	r16, 0x0C	; 12
 128:	90 f1       	brcs	.+100    	; 0x18e <RC5_Error4>
 12a:	07 51       	subi	r16, 0x17	; 23
 12c:	f8 f0       	brcs	.+62     	; 0x16c <RC5_ShortBit4>
 12e:	07 51       	subi	r16, 0x17	; 23
 130:	d8 f0       	brcs	.+54     	; 0x168 <RC5_LongBit4>
 132:	1f 70       	andi	r17, 0x0F	; 15
 134:	61 f5       	brne	.+88     	; 0x18e <RC5_Error4>
 136:	00 91 7e 00 	lds	r16, 0x007E
 13a:	00 2e       	mov	r0, r16
 13c:	0f 73       	andi	r16, 0x3F	; 63
 13e:	00 93 7b 00 	sts	0x007B, r16
 142:	00 2d       	mov	r16, r0
 144:	00 1f       	adc	r16, r16
 146:	00 1f       	adc	r16, r16
 148:	00 1f       	adc	r16, r16
 14a:	03 70       	andi	r16, 0x03	; 3
 14c:	00 93 7a 00 	sts	0x007A, r16
 150:	00 91 7f 00 	lds	r16, 0x007F
 154:	0f 71       	andi	r16, 0x1F	; 31
 156:	00 0f       	add	r16, r16
 158:	00 0f       	add	r16, r16
 15a:	00 90 7b 00 	lds	r0, 0x007B
 15e:	00 2a       	or	r0, r16
 160:	00 92 7b 00 	sts	0x007B, r0
 164:	10 61       	ori	r17, 0x10	; 16
 166:	14 c0       	rjmp	.+40     	; 0x190 <RC5_End4>


rol turns into adc and lsl into add. Processor is attiny2313

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