Verilog Tool Framework / Bugs

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# Sort A -> Z Sort Z -> A	Summary▾ Sort A -> Z Sort Z -> A	Milestone▾ Sort A -> Z Sort Z -> A Filter by Milestone	Status▾ Sort A -> Z Sort Z -> A Filter by Status	Created▾ Sort A -> Z Sort Z -> A	Updated▾ Sort A -> Z Sort Z -> A
6	undefined order of static init causes coredump	None	open	2013-03-23	2013-03-23
5	missing argument to RegisterWarning causes SIGSEGV	None	open	2013-03-23	2013-03-23
4	_NULL define causes compilation error in cygwin	None	open	2012-10-24	2012-10-24
3	xprop mistakenly changes the signedness of expressions	None	open	2011-09-04	2011-09-04
2	Enhancement suggestion	v1.0 (example)	open	2009-04-28	2009-04-28