#2 Enhancement suggestion

[Anonymous]

Hello,

[Q1] In vrq-1.0.49/src/lex.ll

1089 void CompilerDirective( char* line )

1096
1097 if( !strncmp( "`celldefine", line, directiveLen ) ) {
1098 compilerDirectiveCell = 1;
1099 } else if( !strncmp( "`endcelldefine", line, directiveLen ) ) {
1100 compilerDirectiveCell = 1;

Should Line1100 be "compilerDirectiveCell = 0" ?
Otherwise, it will cause top module being of "celldefine" also when previous file has "`celldefine" .

[Q2] In vrq-1.0.49/src/cdumpverilog.cc

2993 static void DumpModule( FILE* f, CModule* module )
2994 {
2995
2996 currentModule = module;

Should Line2995 be inserted with "if(module->Cell()) {return;}" ?
Otherwise, it will dump unnecessary primitive & celldefine which user isn't interested.
Or, could it be another "+dump-without-celldefine" in compiler directive option instead ?

-- chester
feelureal@yahoo.com.tw