#1665 Wrong behaviour of FE3 RAM/ROM mode

[Simon Rowe]

The implementation of Final Expansion 3 RAM/ROM mode does not seem to match real hardware. From experimentation this mode behaves as follows

• writes always go to RAM. If the low order bit in $9c02 for a block is clear the write goes to bank 1 otherwise to bank 2
• reads come from RAM bank 1 if the low order bit is clear otherwise from flash bank 0

I've created a test program that

• writes '1' to the start of BLK5 in RAM bank 1
• writes '2' to the start of BLK5 in RAM bank 2
• In RAM/ROM mode with the low order bit of bank 5 clear writes to $a001
• In RAM/ROM mode with the low order bit of bank 5 set writes to $a000
• In RAM/ROM mode with the low order bit of bank 5 set reads $a000
• In RAM/ROM mode with the low order bit of bank 5 clear reads $a000
• Displays the start of BLK5 in RAM bank 2

With the attached patch xvic now behaves identically to real hardware.

[Simon Rowe]

Patch against 3.6.0

[Simon Rowe]

Output that matches real hardware.

[gpz]

it would be really nice if you could modify the test program so that it can be started by RUN, and then compares the output against the expected value, and changes border color to green or red depending on success/failure - then we can use it in the automatic testbench

i tried to do it quickly, but my vic20 experience is really limited and i dont have a FE to confirm it still works, so better if someone who has that does this :)

[Simon Rowe]

Sure, will look at doing that tomorrow

[Simon Rowe]

Updated test program

[gpz]

patch applied in r41573 - thanks!