A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.

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Categories

Simulation, Education

License

BSD License

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Additional Project Details

Operating Systems

Linux, Solaris, Windows

Languages

English

Intended Audience

Advanced End Users, Developers, End Users/Desktop, Information Technology, Other Audience, Quality Engineers

User Interface

Command-line

Programming Language

Java, VHDL/Verilog

Related Categories

VHDL/Verilog Simulation Software, VHDL/Verilog Education Software, Java Simulation Software, Java Education Software

Registered

2009-08-21
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